summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2012-09-19AddrRange: Simplify Range by removing stream input/outputAndreas Hansson
This patch simplifies the Range class in preparation for the introduction of a more specific AddrRange class that allows interleaving/striping. The only place where the parsing was used was in the unit test.
2012-09-19AddrRange: Remove unused range_multimapAndreas Hansson
This patch simply removes the unused range_multimap in preparation for a more specific AddrRangeMap that also allows interleaving in addition to pure ranges.
2012-09-19AddrRange: Simplify AddrRange params Python hierarchyAndreas Hansson
This patch simplifies the Range object hierarchy in preparation for an address range class that also allows striping (e.g. selecting a few bits as matching in addition to the range). To extend the AddrRange class to an AddrRegion, the first step is to simplify the hierarchy such that we can make it as lean as possible before adding the new functionality. The only class using Range and MetaRange is AddrRange, and the three classes are now collapsed into one.
2012-09-18ruby: eliminate typedef integer_tNilay Vaish
2012-09-18ruby: avoid using g_system_ptr for event schedulingNilay Vaish
This patch removes the use of g_system_ptr for event scheduling. Each consumer object now needs to specify upfront an EventManager object it would use for scheduling events. This makes the ruby memory system more amenable for a multi-threaded simulation.
2012-09-18Stats: Update stats to reflect SimpleMemory bandwidthAndreas Hansson
This patch simply bumps the stats to reflect the introduction of a bandwidth limit of 12.8GB/s for SimpleMemory.
2012-09-18Mem: Add a maximum bandwidth to SimpleMemoryAndreas Hansson
This patch makes a minor addition to the SimpleMemory by enforcing a maximum data rate. The bandwidth is configurable, and a reasonable value (12.8GB/s) has been choosen as the default. The changes do add some complexity to the SimpleMemory, but they should definitely be justifiable as this enables a far more realistic setup using even this simple memory controller. The rate regulation is done for reads and writes combined to reflect the bidirectional data busses used by most (if not all) relevant memories. Moreover, the regulation is done per packet as opposed to long term, as it is the short term data rate (data bus width times frequency) that is the limiting factor. A follow-up patch bumps the stats for the regressions.
2012-09-14gcc: Enable Link-Time Optimization for gcc >= 4.6Andreas Hansson
This patch adds Link-Time Optimization when building the fast target using gcc >= 4.6, and adds a scons flag to disable it (-no-lto). No check is performed to guarantee that the linker supports LTO and use of the linker plugin, so the user has to ensure that binutils GNU ld >= 2.21 or the gold linker is available. Typically, if gcc >= 4.6 is available, the latter should not be a problem. Currently the LTO option is only useful for gcc >= 4.6, due to the limited support on clang and earlier versions of gcc. The intention is to also add support for clang once the LTO integration matures. The same number of jobs is used for the parallel phase of LTO as the jobs specified on the scons command line, using the -flto=n flag that was introduced with gcc 4.6. The gold linker also supports concurrent and incremental linking, but this is not used at this point. The compilation and linking time is increased by almost 50% on average, although ARM seems to be particularly demanding with an increase of almost 100%. Also beware when using this as gcc uses a tremendous amount of memory and temp space in the process. You have been warned. After some careful consideration, and plenty discussions, the flag is only added to the fast target, and the warning that was issued in an earlier version of this patch is now removed. Similarly, the flag used to enable LTO, now the default is to use it, and the flag has been modified to disable LTO. The rationale behind this decision is that opt is used for development, whereas fast is only used for long runs, e.g. regressions or more elaborate experiments where the additional compile and link time is amortized by a much larger run time. When it comes to the return on investment, the regression seems to be roughly 15% faster with LTO. For a bit more detail, I ran twolf on ARM.fast, with three repeated runs, and they all finish within 42 minutes (+- 25 seconds) without LTO and 31 minutes (+- 25 seconds) with LTO, i.e. LTO gives an impressive >25% speed-up for this case. Without LTO (ARM.fast twolf) real 42m37.632s user 42m34.448s sys 0m0.390s real 41m51.793s user 41m50.384s sys 0m0.131s real 41m45.491s user 41m39.791s sys 0m0.139s With LTO (ARM.fast twolf) real 30m33.588s user 30m5.701s sys 0m0.141s real 31m27.791s user 31m24.674s sys 0m0.111s real 31m25.500s user 31m16.731s sys 0m0.106s
2012-09-14scons: Add a target for google-perftools profilingAndreas Hansson
This patch adds a new target called 'perf' that facilitates profiling using google perftools rather than gprof. The perftools CPU profiler offers plenty useful information in addition to gprof, and the latter is kept mostly to offer profiling also on non-Linux hosts.
2012-09-14scons: Restructure ccflags and ldflagsAndreas Hansson
This patch restructures the ccflags such that the common parts are defined in a single location, also capturing all the target types in a single place. The patch also adds a corresponding ldflags in preparation for google-perf profiling support and the addition of Link-Time Optimization.
2012-09-14scons: Use c++0x with gcc >= 4.4 instead of 4.6Andreas Hansson
This patch shifts the version of gcc for which we enable c++0x from 4.6 to 4.4 The more long term plan is to see what the c++0x features can bring and what level of support would be enabled simply by bumping the required version of gcc from 4.3 to 4.4. A few minor things had to be fixed in the code base, most notably the choice of a hashmap implementation. In the Ruby Sequencer there were also a few minor issues that gcc 4.4 was not too happy about.
2012-09-13Stats: Remove the reference stats that are no longer presentAndreas Hansson
This patch simply removes the commitCommittedInsts and commitCommittedOps from the reference statistics, following their removal from the CPU.
2012-09-12se.py Ruby: Connect TLB walker portsJoel Hestness
In order to ensure correct functionality of switch CPUs, the TLB walker ports must be connected to the Ruby system in x86 simulation. This fixes x86 assertion failures that the TLB walker ports are not connected during the CPU switch process.
2012-09-12Standard Switch: Drain the system before switching CPUsJoel Hestness
When switching from an atomic CPU to any of the timing CPUs, a drain is unnecessary since no events are scheduled in atomic mode. However, when trying to switch CPUs starting with a timing CPU, there may be events scheduled. This change ensures that all events are drained from the system by calling m5.drain before switching CPUs.
2012-09-12Base CPU: Initialize profileEvent to NULLJoel Hestness
The profileEvent pointer is tested against NULL in various places, but it is not initialized unless running in full-system mode. In SE mode, this can result in segmentation faults when profileEvent default intializes to something other than NULL.
2012-09-12Ruby: Modify Scons so that we can put .sm files in extrasJason Power
Also allows for header files which are required in slicc generated code to be in a directory other than src/mem/ruby/slicc_interface.
2012-09-12stats: remove duplicate instruction stats from the commit stageAnthony Gutierrez
these stats are duplicates of insts/opsCommitted, cause confusion, and are poorly named.
2012-09-11se.py: removes error in passing options to a binaryNilay Vaish
2012-09-11clang: Fix issues identified by the clang static analyzerAndreas Hansson
This patch addresses a few minor issues reported by the clang static analyzer. The analysis was run with: scan-build -disable-checker deadcode \ -enable-checker experimental.core \ -disable-checker experimental.core.CastToStruct \ -enable-checker experimental.cpluscplus
2012-09-11Checkpoint: Pass maxtick to avoid undefined variableAndreas Hansson
This patch fixes a bug in scriptCheckpoints, where maxtick was used undefined. The bug caused checkpointing by means of --take-checkpoints to fail.
2012-09-11Cache: Split invalidateBlk up to seperate block vs. tagsLena Olson
This seperates the functionality to clear the state in a block into blk.hh and the functionality to udpate the tag information into the tags. This gets rid of the case where calling invalidateBlk on an already-invalid block does something different than calling it on a valid block, which was confusing.
2012-09-11x86 Regressions: Update stats due to register predicationNilay Vaish
2012-09-11X86: make use of register predicationNilay Vaish
The patch introduces two predicates for condition code registers -- one tests if a register needs to be read, the other tests whether a register needs to be written to. These predicates are evaluated twice -- during construction of the microop and during its execution. Register reads and writes are elided depending on how the predicates evaluate.
2012-09-11x86: Add a separate register for D flag bitNilay Vaish
The D flag bit is part of the cc flag bit register currently. But since it is not being used any where in the implementation, it creates an unnecessary dependency. Hence, it is being moved to a separate register.
2012-06-03ISA Parser: Allow predication of source and destination registersNilay Vaish
This patch is meant for allowing predicated reads and writes. Note that this predication is different from the ISA provided predication. They way we currently provide the ISA description for X86, we read/write registers that do not need to be actually read/written. This is likely to be true for other ISAs as well. This patch allows for read and write predicates to be associated with operands. It allows for the register indices for source and destination registers to be decided at the time when the microop is constructed. The run time indicies come in to play only when the at least one of the predicates has been provided. This patch will not affect any of the ISAs that do not provide these predicates. Also the patch assumes that the order in which operands appear in any function of the microop is same across all the functions of the microops. A subsequent patch will enable predication for the x86 ISA.
2012-09-11Ruby: Use uint32_t instead of uint32 everywhereNilay Vaish
2012-09-11Ruby: Use uint8_t instead of uint8 everywhereNilay Vaish
2012-09-10Regression: Updates due to changes to Ruby memory controllerNilay Vaish
2012-09-10Ruby System: Convert to Clocked ObjectNilay Vaish
This patch moves Ruby System from being a SimObject to recently introduced ClockedObject.
2012-09-10Ruby Slicc: remove the call to cin.get() functionNilay Vaish
If I understand correctly, this was put in place so that a debugger can be attached when the protocol aborts. While this sounds useful, it is a problem when the simulation is not being actively monitored. I think it is better to remove this.
2012-09-10Ruby: Bump the stats after recent memory controller changesAndreas Hansson
This patch simply bumps the stats to avoid having failing regressions. Someone with more insight in the changes should verify that these differences all make sense.
2012-09-10Mem: Allow serializing of more than INT_MAX bytesMarco Elver
Despite gzwrite taking an unsigned for length, it returns an int for bytes written; gzwrite fails if (int)len < 0. Because of this, call gzwrite with len no larger than INT_MAX: write in blocks of INT_MAX if data to be written is larger than INT_MAX.
2012-09-10NetBSD: Build on NetBSDPalle Lyckegaard
Minor patch against so building on NetBSD is possible.
2012-09-10AddrRange: Remove the unused range_ops headerAndreas Hansson
This patch prunes the range_ops header that is no longer used. The bridge used it to do filtering of address ranges, but this is changed since quite some time. Ultimately this patch aims to simplify the handling of ranges before specialising the AddrRange to an AddrRegion that also allows striping bits to be selected.
2012-09-10Inet: Remove the SackRange and its useAndreas Hansson
This patch aims to simplify the use of the Range class before introducing a more elaborate AddrRegion to replace the AddrRange. The SackRange is the only use of the range class besides address ranges, and the removal of this use makes for an easier modification of the range class. The functionlity that is removed with this patch is not used anywhere throughout the code base.
2012-09-10Device: Update stats for PIO and PCI latency changeAndreas Hansson
This patch merely updates the regression stats to reflect the change in PIO and PCI latency.
2012-09-10Device: Bump PIO and PCI latencies to more reasonable valuesAndreas Hansson
This patch addresses a previously highlighted issue with the default latencies used for PIO and PCI devices. The values are merely educated guesses and might not represent the particular system you want to model. However, the values in this patch are definitely far more realistic than the previous ones. In i8254xGBe, the writeConfig method is updated to use configDelay instead of pioDelay. A follow-up patch will update the regression stats.
2012-09-09se.py: support specifying multiple programs via command lineNilay Vaish
This patch allows for specifying multiple programs via command line. It also adds an option for specifying whether to use of SMT. But SMT does not work for the o3 cpu as of now.
2012-09-07sim: Update the SimObject documentationAndreas Sandberg
Includes a small change in sim_object.cc that adds the name space to the output stream parameter in serializeAll. Leaving out the name space unfortunately confuses Doxygen.
2012-09-07sim: Remove the unused SimObject::regFormulas methodAndreas Sandberg
Simulation objects normally register derived statistics, presumably what regFormulas originally was meant for, in regStats(). This patch removes regRegformulas since there is no need to have a separate method call to register formulas.
2012-09-07O3: Get rid of incorrect assert in RAS.Ali Saidi
2012-09-07dev: Fix bifield definition in timer_cpulocal.hhAli Saidi
Bitfield definition in the local timer model for ARM had the bitfield range numbers reversed which could lead to buggy behavior.
2012-09-07ARM: Fix the compiler and platform identification for building on ARM.Ali Saidi
2012-09-07ARM: fix m5 op binary to properly convert 64bit operandsAli Saidi
2012-09-07ARM: Fix issue with with way MPIDR is read to include affinity levels.Matt Evans
The simple_bootloader checks for CPU0 in a manner incompatible with systems actually using affinity levels -- just looking at MPIDR[7:0]. However, in future we may wish to use real affinity levels and this method will be in danger of matching several CPUs with affinity0 = 0. Match affinity2 == affinity1 == affinity0 == 0 instead.
2012-09-07Igbe: Newer kernels seem to allow TSO headers and packet data to be in one descAli Saidi
Implement some code we used to panic on as it actually does happen with the e1000 driver in Linux 3.3+. We used to assume that a TSO header would never be part of a larger payload, however it appears as though it now can be.
2012-09-07CPU: O3-PipeView.py doesn't display the end of timelines.Djordje Kovacevic
Insts' timeline that stretches over multiple lines doesn't always get printed.
2012-09-07sim: add validation to make sure there is memory where we're loading the kernelKrishnendra Nathella
2012-09-07loader: initialize all memory in the ObjectFile objects.Ali Saidi
Some bare metal build flows seem to build binaries that we aren't necessarily expecting. Initialize everything to 0, so we don't make any assumptions about what is or isn't in the binary.
2012-09-07ARM: Fix one of the timers used in the VExpress EMM platform.Ali Saidi
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 11:34:24 +0000