gem5 - gem5

Age	Commit message (Expand)	Author
2010-12-30	style: make style hook work with pre-qrefresh and update to use new code	Nathan Binkert
2010-12-23	PerfectCacheMemory: Add return statements to two functions.	Nilay Vaish
2010-12-22	This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh f...	Nilay Vaish
2010-12-21	memtest: delete some crufty dead code	Steve Reinhardt
2010-12-21	Get rid of unused file src/base/dbl_list.hh	Steve Reinhardt
2010-12-21	stats: allow stats to be reset even if no objects have been instantiated	Nathan Binkert
2010-12-21	importer: fix error message	Nathan Binkert
2010-12-21	scons: remove extra dependencies	Nathan Binkert
2010-12-20	Style: Replace some tabs with spaces.	Gabe Black
2010-12-20	Params: Fix a broken error message in verifyIp.	Gabe Black
2010-12-09	ARM: Take advantage of new PCState syntax.	Gabe Black
2010-12-09	ARM: Get rid of some unused FP operands.	Gabe Black
2010-12-08	Merge.	Gabe Black
2010-12-08	ruby: remove Ruby asserts for m5.fast	Brad Beckmann
2010-12-08	Alpha: Take advantage of new PCState syntax.	Gabe Black
2010-12-08	MIPS: Take advantage of new PCState syntax.	Gabe Black
2010-12-08	POWER: Take advantage of new PCState syntax.	Gabe Black
2010-12-08	SPARC: Take advantage of new PCState syntax.	Gabe Black
2010-12-08	X86: Take advantage of new PCState syntax.	Gabe Black
2010-12-07	ISA: Get the parser to support pc state components more elegantly.	Gabe Black
2010-12-07	Configs: Automatically choose the correct hello world binary.	Ali Saidi
2010-12-07	O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).	Ali Saidi
2010-12-07	Stats: Fix stats for cumulative flags change.	Ali Saidi
2010-12-07	O3: Support squashing all state after special instruction	Ali Saidi
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-12-07	O3: Support SWAP and predicated loads/store in ARM.	Min Kyu Jeong
2010-12-07	ARM: Support switchover with hardware table walkers	Ali Saidi
2010-12-01	ruby: Converted old ruby debug calls to M5 debug calls	Nilay Vaish
2010-11-26	IGbE: return 0 on an invalid descriptor size instead of -1.	Ali Saidi
2010-11-23	Copyright: Add AMD copyright to the param changes I just made.	Gabe Black
2010-11-23	Params: Add parameter types for IP addresses in various forms.	Gabe Black
2010-11-23	X86: Loosen an assert for x86 and connect the APIC ports when caches are used.	Gabe Black
2010-11-23	X86: Obey the PCD (cache disable) bit in the page tables.	Gabe Black
2010-11-22	X86: Mark IO space accesses as uncachable.	Gabe Black
2010-11-22	X86: Remove reserved* from the m5 utility program for x86.	Gabe Black
2010-11-22	IDE,X86: Fix IDE controller BAR configuration for x86.	Gabe Black
2010-11-20	random: small comment about our random number generator and its origin	Nathan Binkert
2010-11-19	SE: Fix simulating more than 4GB of RAM in SE mode	Ali Saidi
2010-11-19	SCons: Fix compilation on OS X	Ali Saidi
2010-11-19	SCons: Support building without an ISA	Ali Saidi
2010-11-18	O3: Fix fp destination register flattening, and index offset adjusting.	Gabe Black
2010-11-17	Config: Change misleading "cycle" message to say "tick".	Gabe Black
2010-11-15	Stats: Update the O3 fetch stats for SPARC.	Gabe Black
2010-11-15	O3: Make O3 support variably lengthed instructions.	Gabe Black
2010-11-15	O3: reset architetural state by calling clear()	Ali Saidi
2010-11-15	ARM: Add comment about the organization of the IT state register	Ali Saidi
2010-11-15	Regressions: Update regressions for SIMD opclass changes	Ali Saidi
2010-11-15	CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.	Giacomo Gabrielli
2010-11-15	ARM: Compile O3 CPU by default	Ali Saidi
2010-11-15	O3: prevent a squash when completeAcc() modifies misc reg through TC.	Min Kyu Jeong