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AgeCommit message (Collapse)Author
2011-02-07X86: Fix compiling vtophys.ccGabe Black
2011-02-06regress: Regression Tester output updatesBrad Beckmann
2011-02-06ruby: support to stallAndWait the mandatory queueBrad Beckmann
By stalling and waiting the mandatory queue instead of recycling it, one can ensure that no incoming messages are starved when the mandatory queue puts signficant of pressure on the L1 cache controller (i.e. the ruby memtester). --HG-- rename : src/mem/slicc/ast/WakeUpDependentsStatementAST.py => src/mem/slicc/ast/WakeUpAllDependentsStatementAST.py
2011-02-06ruby: minor fix to deadlock panic messageBrad Beckmann
2011-02-06boot: script that creates a checkpoint after Linux boot upBrad Beckmann
2011-02-06garnet: Split network power in ruby.statsJoel Hestness
Split out dynamic and static power numbers for printing to ruby.stats
2011-02-06MOESI_hammer: fixed dir bug counting received acksBrad Beckmann
2011-02-06ruby: numa bit fix for sparse memoryBrad Beckmann
2011-02-06MOESI_CMP_token: removed unused message fieldsTushar Krishna
2011-02-06mem: Added support for Null data packetBrad Beckmann
The packet now identifies whether static or dynamic data has been allocated and is used by Ruby to determine whehter to copy the data pointer into the ruby request. Subsequently, Ruby can be told not to update phys memory when receiving packets.
2011-02-06m5: added work completed monitoring supportBrad Beckmann
2011-02-06dev: fixed bugs to extend interrupt capability beyond 15 coresBrad Beckmann
2011-02-06x86: Timing support for pagetable walkerJoel Hestness
Move page table walker state to its own object type, and make the walker instantiate state for each outstanding walk. By storing the states in a queue, the walker is able to handle multiple outstanding timing requests. Note that functional walks use separate state elements.
2011-02-06TimingSimpleCPU: split data sender state fixJoel Hestness
In sendSplitData, keep a pointer to the senderState that may be updated after the call to handle*Packet. This way, if the receiver updates the packet senderState, it can still be accessed in sendSplitData.
2011-02-06ruby: Fix RubyPort to properly handle retrysBrad Beckmann
2011-02-06Ruby: Fix to return cache block size to CPU for split data transfersJoel Hestness
2011-02-06Ruby: Add support for locked memory accesses in X86_FSJoel Hestness
2011-02-06Ruby: Update the Ruby request type names for LL/SCJoel Hestness
2011-02-06ruby: Assert for x86 misaligned accessBrad Beckmann
This patch ensures only aligned access are passed to ruby and includes a fix to the DPRINTF address print.
2011-02-06ruby: x86 fs config supportBrad Beckmann
2011-02-06MOESI_hammer: Added full-bit directory supportBrad Beckmann
2011-02-06x86: Add checkpointing capability to devicesJoel Hestness
Add checkpointing capability to the Intel 8254 timer, CMOS, I8042, PS2 Keyboard and Mouse, I82094AA, I8237, I8254, I8259, and speaker devices
2011-02-06x86: Add checkpointing capability to arch componentsJoel Hestness
Add checkpointing capability to the x86 interrupt device and the TLBs
2011-02-06x86: implements vtophysJoel Hestness
Calls walker to look up virt. to phys. page mapping
2011-02-06IntDev: packet latency fixJoel Hestness
The x86 local apic now includes a separate latency parameter for interrupts.
2011-02-06MessagePort: implement the virtual recvTiming function to avoid double pkt ↵Joel Hestness
delete Double packet delete problem is due to an interrupt device deleting a packet that the SimpleTimingPort also deletes. Since MessagePort descends from SimpleTimingPort, simply reimplement the failing code from SimpleTimingPort: recvTiming.
2011-02-06MOESI_hammer: trigge queue fix.Joel Hestness
2011-02-06mcpat: Adds McPAT performance countersJoel Hestness
Updated patches from Rick Strong's set that modify performance counters for McPAT
2011-02-06garnet: added orion2.0 for network power calculationTushar Krishna
2011-02-06garnet: separate data and ctrl VCsTushar Krishna
Separate data VCs and ctrl VCs in garnet, as ctrl VCs have 1 buffer per VC, while data VCs have > 1 buffers per VC. This is for correct power estimations.
2011-02-06x86: set IsCondControl flag for the appropriate microopsBrad Beckmann
2011-02-05X86: Add o3 regressions in SE mode.Gabe Black
Exclude bzip2 for now. It works, it just takes too long to run.
2011-02-04X86: Update ruby stats for stupd change.Gabe Black
2011-02-03Fault: Forgot to refresh to grab these header guard updates.Gabe Black
2011-02-04imported patch regression_updatesKorey Sewell
2011-02-04inorder: fault handlingKorey Sewell
Maintain all information about an instruction's fault in the DynInst object rather than any cpu-request object. Also, if there is a fault during the execution stage then just save the fault inside the instruction and trap once the instruction tries to graduate
2011-02-04inorder: pcstate and delay slots bugKorey Sewell
not taken delay slots were not being advanced correctly to pc+8, so for those ISAs we 'advance()' the pcstate one more time for the desired effect
2011-02-04inorder: add a fetch buffer to fetch unitKorey Sewell
Give fetch unit it's own parameterizable fetch buffer to read from. Very inefficient (architecturally and in simulation) to continually fetch at the granularity of the wordsize. As expected, the number of fetch memory requests drops dramatically
2011-02-04inorder: overload find-req fnKorey Sewell
no need to have separate function name findSplitRequest, just overload the function
2011-02-04inorder: implement separate fetch unitKorey Sewell
instead of having one cache-unit class be responsible for both data and code accesses, separate code that is just for fetch in it's own derived class off the original base class. This makes the code easier to manage as well as handle future cases of special fetch handling
2011-02-04inorder: cache port blockingKorey Sewell
set the request to false when the cache port blocks so we dont deadlock. also, comment out the outstanding address list sanity check for now.
2011-02-04inorder: stage width as a python parameterKorey Sewell
allow the user to specify how many instructions a pipeline stage can process on any given cycle (stageWidth...i.e.bandwidth) by setting the parameter through the python interface rather than compile the code after changing the *.cc file. (we always had the parameter there, but still used the static 'ThePipeline::StageWidth' instead) - Since StageWidth is now dynamically defined, change the interstage communication structure to use a vector and get rid of array and array handling index (toNextStageIndex) since we can just make calls to the list for the same information
2011-02-04inorder: multi-issue branch resolutionKorey Sewell
Only execute (resolve) one branch per cycle because handling more than one is a little more complicated
2011-02-04inorder: pipe. stage inst. bufferingKorey Sewell
use skidbuffer as only location for instructions between stages. before, we had the insts queue from the prior stage and the skidbuffer for the current stage, but that gets confusing and this consolidation helps when handling squash cases
2011-02-04inorder: change skidBuffer to list instead of queueKorey Sewell
manage insertion and deletion like a queue but will need access to internal elements for future changes Currently, skidbuffer manages any instruction that was in a stage but could not complete processing, however we will want to manage all blocked instructions (from prev stage and from cur. stage) in just one buffer.
2011-02-04inorder: activity tracking bugKorey Sewell
Previous code was marking CPU activity on almost every cycle due to a bug in tracking the status of pipeline stages. This disables the CPU from sleeping on long latency stalls and increases simulation time
2011-02-03Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.Gabe Black
--HG-- rename : src/sim/fault.hh => src/sim/fault_fwd.hh
2011-02-03Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.Gabe Black
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches.
2011-02-02O3: Fix a style bug in O3.Gabe Black