summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2012-09-12Base CPU: Initialize profileEvent to NULLJoel Hestness
2012-09-12Ruby: Modify Scons so that we can put .sm files in extrasJason Power
2012-09-12stats: remove duplicate instruction stats from the commit stageAnthony Gutierrez
2012-09-11se.py: removes error in passing options to a binaryNilay Vaish
2012-09-11clang: Fix issues identified by the clang static analyzerAndreas Hansson
2012-09-11Checkpoint: Pass maxtick to avoid undefined variableAndreas Hansson
2012-09-11Cache: Split invalidateBlk up to seperate block vs. tagsLena Olson
2012-09-11x86 Regressions: Update stats due to register predicationNilay Vaish
2012-09-11X86: make use of register predicationNilay Vaish
2012-09-11x86: Add a separate register for D flag bitNilay Vaish
2012-06-03ISA Parser: Allow predication of source and destination registersNilay Vaish
2012-09-11Ruby: Use uint32_t instead of uint32 everywhereNilay Vaish
2012-09-11Ruby: Use uint8_t instead of uint8 everywhereNilay Vaish
2012-09-10Regression: Updates due to changes to Ruby memory controllerNilay Vaish
2012-09-10Ruby System: Convert to Clocked ObjectNilay Vaish
2012-09-10Ruby Slicc: remove the call to cin.get() functionNilay Vaish
2012-09-10Ruby: Bump the stats after recent memory controller changesAndreas Hansson
2012-09-10Mem: Allow serializing of more than INT_MAX bytesMarco Elver
2012-09-10NetBSD: Build on NetBSDPalle Lyckegaard
2012-09-10AddrRange: Remove the unused range_ops headerAndreas Hansson
2012-09-10Inet: Remove the SackRange and its useAndreas Hansson
2012-09-10Device: Update stats for PIO and PCI latency changeAndreas Hansson
2012-09-10Device: Bump PIO and PCI latencies to more reasonable valuesAndreas Hansson
2012-09-09se.py: support specifying multiple programs via command lineNilay Vaish
2012-09-07sim: Update the SimObject documentationAndreas Sandberg
2012-09-07sim: Remove the unused SimObject::regFormulas methodAndreas Sandberg
2012-09-07O3: Get rid of incorrect assert in RAS.Ali Saidi
2012-09-07dev: Fix bifield definition in timer_cpulocal.hhAli Saidi
2012-09-07ARM: Fix the compiler and platform identification for building on ARM.Ali Saidi
2012-09-07ARM: fix m5 op binary to properly convert 64bit operandsAli Saidi
2012-09-07ARM: Fix issue with with way MPIDR is read to include affinity levels.Matt Evans
2012-09-07Igbe: Newer kernels seem to allow TSO headers and packet data to be in one descAli Saidi
2012-09-07CPU: O3-PipeView.py doesn't display the end of timelines.Djordje Kovacevic
2012-09-07sim: add validation to make sure there is memory where we're loading the kernelKrishnendra Nathella
2012-09-07loader: initialize all memory in the ObjectFile objects.Ali Saidi
2012-09-07ARM: Fix one of the timers used in the VExpress EMM platform.Ali Saidi
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-09-05stats: Update Ruby regressions for memory controller fixJoel Hestness
2012-09-05Ruby Memory Controller: Fix clockingJoel Hestness
2012-08-28Ruby: Correct DataBlock =operatorJason Power
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-08-28Port: Stricter port bind/unbind semanticsAndreas Hansson
2012-08-28Checker: Bump the realview-o3-checker regressionAndreas Hansson
2012-08-28Checker: Fix checker CPU portsAndreas Hansson
2012-08-28swig: Disable unused value warning with llvm 3.1 compilersAndreas Hansson
2012-08-27sim: fix overflow check in simulate because Tick is now unsignedAnthony Gutierrez
2012-08-27Ruby: remove README.debugging and Decommissioning_noteNilay Vaish
2012-08-27System: Remove redundant call to startupCPUNilay Vaish
2012-08-27Ruby: Remove RubyEventQueueNilay Vaish