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2015-04-24misc: Appease gcc 5.1 without moving GDB_REG_BYTESAndreas Hansson
This patch rolls back the move of the GDB_REG_BYTES constant, and instead adds M5_VAR_USED.
2015-04-23config: enable setting SE-mode environment variables from filebpotter
2015-04-23arm, dev: Add a UFS deviceRene de Jong
This patch introduces a UFS host controller and a UFS device. More information about the UFS standard can be found at the JEDEC site: http://www.jedec.org/standards-documents/results/jesd220 Note that the model does not implement the complete standard, and as such is not an actual implementation of UFS. The following SCSI commands are implemented: inquiry, read, read capacity, report LUNs, start/stop, test unit ready, verify, write, format unit, send diagnostic, synchronize cache, mode select, mode sense, request sense, unmap, write buffer and read buffer. This is sufficient for usage with Linux and Android. To interact with this model a kernel version 3.9 or above is needed.
2015-04-23arm, dev: Add a NAND flash timing modelRene de Jong
This adds a NAND flash timing model. This model takes the number of planes into account and is ultimately intended to be used as a high-level performance model for any device using flash. To access the memory, use either readMemory or writeMemory. To make use of the model you will need an interface model such as UFSHostDevice, which is part of a separate patch. At the moment the flash device is part of the ARM device tree since the only use if the UFSHostDevice, and that in turn relies on the ARM GIC.
2015-04-23dev: Add support for i2c devicesPeter Enns
This patch adds an I2C bus and base device. I2C is used to connect a variety of sensors, and this patch serves as a starting point to enable a range of I2C devices.
2015-04-23misc: Appease gcc 5.1Andreas Hansson
This patch fixes a few small issues to ensure gem5 compiles when using gcc 5.1. First, the GDB_REG_BYTES in the RemoteGDB header are, rather surprisingly, flagged as unused for both ARM and X86. Removing them, however, causes compilation errors as they are actually used in the source file. Moving the constant into the class definition fixes the issue. Possibly a gcc bug. Second, we have an unused EthPktData constructor using auto_ptr, and the latter is deprecated. Since the code is never used it is simply removed.
2015-04-22stats: update for previous changesetSteve Reinhardt
Very small differences in IQ-specific O3 stats.
2015-04-22cpu: remove conditional check (count > 0) on o3 IQ squashesBrandon Potter
The o3 cpu instruction queue model uses the count variable to track the number of unissued instructions in the queue. Previously, the squash method used this variable to avoid executing the doSquash method when there were no unissued instructions in the pipeline. A corner case problem exists when only issued instructions exist in the pipeline and a squash occurs; the doSquash code is not invoked and subsequently does not clean up state properly.
2015-04-22syscall_emul: implement clock_gettime system callBrandon Potter
2015-04-22syscall_emul: update x86 syscall tableMonir Mozumder
Update table with additional definitions through Linux 3.13.
2015-04-22syscall_emul: update getrlimit to use warnBrandon Potter
Don't use std::cerr directly, and just return EINVAL instead of aborting.
2015-04-22syscall_emul: fix warning with wrong syscall nameBrandon Potter
Also nix extra whitespace.
2015-04-22base: add new ChunkGenerator method to identify last chunkBrandon Potter
2015-04-20stats: update a few stats from long O3 runsSteve Reinhardt
Very small changes to iew.predictedNotTakenIncorrect and iew.branchMispredicts. Looks like similar updates were committed on April 3 (changeset 235ff1c046df), but only for the quick tests.
2015-04-20cpu: Remove the InOrderCPU from the treeAndreas Hansson
This patch takes the final step in removing the InOrderCPU from the tree. Rest in peace. The MinorCPU is now used to model an in-order microarchitecture, and long term the MinorCPU will eventually be renamed InOrderCPU.
2015-04-20config: Remove memory aliases and rely on class nameAndreas Hansson
Instead of maintaining two lists, rely entirely on the class name. There is really no point in causing unecessary confusion.
2015-04-15Added tag stable_2015_04_15 for changeset e17949745150Nilay Vaish
2015-04-14stats: x86: changes due to recent patchesNilay Vaish
The change in 20.parser is from new x87 instructions. The change to pc-o3-timing is not clear to me. It seems that this test might be invoking some undefined behavior.
2015-04-14config, cpu: fix progress interval for switched CPUsMalek Musleh
This patch ensures that the CPU progress Event is triggered for the new set of switched_cpus that get scheduled (e.g. during fast-forwarding). it also avoids printing the interval state if the cpu is currently switched out. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-04-13cpu: re-organizes the branch predictor structure.Dibakar Gope
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-04-13x86: implements x87 mult/div instructionsNilay Vaish
2015-04-13ruby: allow restoring from checkpoint when using DRAMCtrlLena Olson
Restoring from a checkpoint with ruby + the DRAMCtrl memory model was not working, because ruby and DRAMCtrl disagreed on the current tick during warmup. Since there is no reason to do timing requests during warmup, use functional requests instead. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-04-13sim: Use NULL instead of None for testing filenames.Nilay Vaish
The filenames are initialized with NULL. So the test should be checking for them to be == NULL instead == None.
2015-04-13sim: fix function for emulating dup()Nilay Vaish
The function was using the host fd to obtain the fd object from the simulated process.
2015-04-08config: Support full-system with SST's memory systemCurtis Dunham
This patch adds an example configuration in ext/sst/tests/ that allows an SST/gem5 instance to simulate a 4-core AArch64 system with SST's memHierarchy components providing all the caches and memories.
2015-04-08ext: Add SST connectorCurtis Dunham
This patch adds a connector that allows gem5 to be used as a component in SST (Structural Simulation Toolkit, sst-simulator.org). At a high level, this allows memory traffic to pass between the two simulators. SST Links are roughly analogous to gem5 Ports, although Links do not have a notion of master and slave. This distinction is important to gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave must be used, and similarly when connecting the memory side of SST cache to a gem5 port (for memory <-> I/O), an ExternalMaster must be used. These connectors handle the administrative aspects of gem5 (initialization, simulation, shutdown) as well as translating SST's MemEvents into gem5 Packets and vice-versa.
2015-04-03stats: updates due to recent changesets.Nilay Vaish
2015-04-03dev: (un)serialize fix for the RTC and RTC Timer Interrupt eventsNikos Nikoleris
Restoring from a checkpoint fails if either the RTC or the RTC Timer Interrrupt event is disabled. The restored machine tried incorrectly to schedule the next event with negative offset. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-04-03sim: correct check for endianessRuslan Bukin
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-04-03dev: Extend access width for IDE control registersRuslan Bukin
Add 32-bit access width for PrimaryTiming register and 16bit for UDMAControl register as FreeBSD required. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-04-03cpu: fix system total instructions accountingNikos Nikoleris
The totalInstructions counter is only incremented when the whole instruction is commited and not on every microop. It was incorrectly reset in atomic and timing cpus. Committed by: Nilay Vaish <nilay@cs.wisc.edu>"
2015-04-03x86: fix debug trace output for mwaitLena Olson
When running with the Exec flag, the mwait instruction attempted to print out its source registers, which were never actually initialized. This led to sporadic assertion failures when the value stored there was invalid. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-03-27arm, configs: Do not forward snoops from I cacheAndreas Hansson
This fix simply tells the I cache to not forward snoops to the fetch unit (since there is really no reason to do so).
2015-03-27mem: Support any number of master-IDs in stride prefetcherStephan Diestelhorst
The stride prefetcher had a hardcoded number of contexts (i.e. master-IDs) that it could handle. Since master IDs need to be unique per system, and every core, cache etc. requires a separate master port, a static limit on these does not make much sense. Instead, this patch adds a small hash map that will map all master IDs to the right prefetch state and dynamically allocates new state for new master IDs.
2015-03-27mem: Allocate cache writebacks before new MSHRsAndreas Hansson
This patch changes the order of writeback allocation such that any writebacks resulting from a tag lookup (e.g. for an uncacheable access), are added to the writebuffer before any new MSHR entries are allocated. This ensures that the writebacks logically precedes the new allocations. The patch also changes the uncacheable flush to use proper timed (or atomic) writebacks, as opposed to functional writes.
2015-03-27mem: Cleanup flow for uncacheable accessesAndreas Hansson
This patch simplifies the code dealing with uncacheable timing accesses, aiming to align it with the existing miss handling. Similar to what we do in atomic, a timing request now goes through Cache::access (where the block is also flushed), and then proceeds to ignore any existing MSHR for the block in question. This unifies the flow for cacheable and uncacheable accesses, and for atomic and timing.
2015-03-27mem: Ignore uncacheable MSHRs when finding matchesAndreas Hansson
This patch changes how we search for matching MSHRs, ignoring any MSHR that is allocated for an uncacheable access. By doing so, this patch fixes a corner case in the MSHRs where incorrect data ended up being copied into a (cacheable) read packet due to a first uncacheable MSHR target of size 4, followed by a cacheable target to the same MSHR of size 64. The latter target was filled with nonsense data.
2015-03-27mem: Remove redundant allocateUncachedReadBuffer in cacheAndreas Hansson
This patch removes the no-longer-needed allocateUncachedReadBuffer. Besides the checks it is exactly the same as allocateMissBuffer and thus provides no value.
2015-03-27mem: Modernise MSHR iterators to C++11Andreas Hansson
This patch updates the iterators in the MSHR and MSHR queues to use C++11 range-based for loops. It also does a bit of additional house keeping.
2015-03-27tests: Update stats for cache block alignmentAndreas Hansson
2015-03-27mem: Align all MSHR entries to block boundariesAndreas Hansson
This patch aligns all MSHR queue entries to block boundaries to simplify checks for matches. Previously there were corner cases that could lead to existing entries not being identified as matches. There are, rather alarmingly, a few regressions that change with this patch.
2015-03-27mem: Rename PREFETCH_SNOOP_SQUASH flag to BLOCK_CACHEDAli Jafri
This patch subsumes the PREFETCH_SNOOP_SQUASH flag with the more generic BLOCK_CACHED flag. Future patches implementing cache eviction messages can use the BLOCK_CACHED flag in almost the same manner as hardware prefetches use the PREFETCH_SNOOP_SQUASH flag. The PREFTECH_SNOOP_FLAG is set if the prefetch target is found in the tags or the MSHRs in any state, so we are simply replacing calls to setPrefetchSquashed() with setBlockCached(). The case of where the prefetch target is found in the writeback MSHRs of upper level caches continues to be covered by the MEM_INHIBIT flag.
2015-03-26sim: Update limit_event reuse to final versionCurtis Dunham
Matching final version on reviewboard.
2015-03-26cpu: Fix InstPBTrace inheritanceAndreas Hansson
This patch fixes an issue that prevented gem5 to be built with C++ config and without Python.
2015-03-23mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMWSteve Reinhardt
Makes x86-style locked operations even more distinct from LLSC operations. Using "locked" by itself should be obviously ambiguous now.
2015-03-23config: expand '~' and '~user' in pathsSteve Reinhardt
2015-03-23misc: quote args in echoed command lineSteve Reinhardt
Currently if there are shell special characters in a command-line argument, you can't copy and paste the echoed command line onto a shell prompt because the characters aren't quoted properly. This patch fixes that problem.
2015-03-23config: Add ability to exit simulation after initializationCurtis Dunham
When using gem5 as a slave simulator, it will not advance the clock on its own and depends on the master simulator calling simulate(). This new option lets us use the Python scripts to do all the configuration while stopping short of actually simulating anything.
2015-03-23sim: Reuse the same limit_event in simulate()Curtis Dunham
This patch accomplishes two things: 1. Makes simulate()'s GlobalSimLoopExitEvent a singleton reused across calls. This is slightly more efficient than recreating it every time. 2. Gives callers to simulate() (especially other simulators) a foolproof way of knowing that the simulation period ended successfully by hitting the limit event. They can call getLimitEvent() and compare it to the return value of simulate(). This change was motivated by an ongoing effort to integrate gem5 and SST, with SST as the master sim and gem5 as the slave sim.
2015-03-23mem: Tidy up RequestAndreas Hansson
This patch does a bit of house keeping, fixing up typos, removing dead code etc.