| Age | Commit message (Expand) | Author |
|---|
| 2017-08-08 | mem-cache: Delete squashed HWPrefetches | Pau Cabre |
| 2017-08-03 | configs, arm: Fix incorrect use of mem_range in bL example | Andreas Sandberg |
| 2017-08-03 | arm, config: Fix CPU names in ARM example configs | Andreas Sandberg |
| 2017-08-02 | base: Give more information when setting up asynchronous IO fails. | Gabe Black |
| 2017-08-01 | misc: git ignore file udpated | Éder F. Zulian |
| 2017-08-01 | style: Add shared gem5 headers to the style checker | Andreas Sandberg |
| 2017-08-01 | util: Move m5op.h to the shared include directory | Andreas Sandberg |
| 2017-08-01 | util, m5: Use consistent naming for m5op C symbols | Andreas Sandberg |
| 2017-08-01 | arch-arm: Use named constants for m5op instructions | Andreas Sandberg |
| 2017-08-01 | sim: Use named constants for pseudo ops | Andreas Sandberg |
| 2017-08-01 | util: Move the m5ops.h file to a shared directory | Andreas Sandberg |
| 2017-08-01 | kvm, arm: Switch to the device EQ when accessing ISA devices | Andreas Sandberg |
| 2017-08-01 | kvm: Add a helper method to access device event queues | Andreas Sandberg |
| 2017-08-01 | cpu, kvm: Fix deadlock issue when resuming a drained system | Andreas Sandberg |
| 2017-08-01 | arch-arm: Switch to DTOnly as the default machine type | Andreas Sandberg |
| 2017-07-28 | config: Discover CPU timing models based on target ISA | Andreas Sandberg |
| 2017-07-27 | config, arm: SE configuration for the ARM starter kit | Gabor Dozsa |
| 2017-07-27 | config, arm: FS configuration for the ARM starter kit | Gabor Dozsa |
| 2017-07-27 | config, arm: Add a high-performance in order timing model | Ashkan Tousi |
| 2017-07-27 | config: Change mem_range attribute naming in ARM SimpleSystem | Gabor Dozsa |
| 2017-07-25 | tests: Fix path for module imports in ARM system configs | Nikos Nikoleris |
| 2017-07-25 | configs,sim-se: fix se.py multi-cpu multi-cmd issue | Pau Cabre |
| 2017-07-20 | sim: Prevent segfault in the wakeCpu m5op if id is invalid | Jose Marinho |
| 2017-07-19 | cpu: Add missing rename of vector registers in the O3 CPU | Rekai Gonzalez-Alberquilla |
| 2017-07-17 | cpu,o3: Fixed checkpointing bug occuring in the o3 CPU | Anouk Van Laer |
| 2017-07-17 | tests: Don't treat new stats as a cause for failures | Andreas Sandberg |
| 2017-07-17 | sim, x86: Make clone a virtual function | Sean Wilson |
| 2017-07-17 | x86: Add stats to X86 TLB | Swapnil Haria |
| 2017-07-17 | riscv: Define register index constants using literals | Alec Roelke |
| 2017-07-14 | riscv: Disambiguate between the C and C++ versions of isnan and isinf. | Gabe Black |
| 2017-07-14 | tests: Upate RISC-V binaries and results | Alec Roelke |
| 2017-07-14 | riscv: Fix bugs with RISC-V decoder and detailed CPUs | Alec Roelke |
| 2017-07-14 | riscv: Add unused attribute to some registers.hh constants | Alec Roelke |
| 2017-07-13 | arch-arm: fix ldm of pc interswitching branch | Gedare Bloom |
| 2017-07-12 | ruby: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | arm: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | dev: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | net: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | testers: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | kvm, mem: Refactor some Event subclasses into lambdas | Sean Wilson |
| 2017-07-12 | cpu: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | gpu-compute: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | sim, gdb: Refactor some Event subclasses into lambdas | Sean Wilson |
| 2017-07-12 | mips, x86: Refactor some Event subclasses into lambdas | Sean Wilson |
| 2017-07-12 | util,arch-arm: Added python script to generate ARM FS binaries | Pau Cabre |
| 2017-07-12 | cpu, sim: Add param to force CPUs to wait for GDB | Jose Marinho |
| 2017-07-11 | arch-riscv,tests: Add insttests for RV64C | Alec Roelke |
| 2017-07-11 | arch-riscv: Add support for compressed extension RV64C | Alec Roelke |
| 2017-07-11 | arch-riscv: Restructure ISA description | Alec Roelke |
| 2017-07-10 | dev-arm: Add ID registers to the GIC model | Jose Marinho |
