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2017-04-28scons: Add a Transform() for when linking shared libraries.Gabe Black
Change-Id: I7ddba0cc7be559633328011c1c7e2282f509b78c Reviewed-on: https://gem5-review.googlesource.com/2943 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-04-28scons: Find ext build directories automatically.Gabe Black
The ext directories with SConscripts in them are easy to find automatically. Avoid boilerplate listing them out and SConscript()ing them manually. Change-Id: Ib723882aebc00e639eb8ec44904bb05ffa2c6b55 Reviewed-on: https://gem5-review.googlesource.com/2942 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-04-25misc: Add MAINTAINERS fileJason Lowe-Power
This file defines all of the commit keywords used for gem5 commits and the maintainter(s) for each of these keywords. This patch introduces a number of new keywords, and changes to previous keywords. The new keywords better follow gem5's directory structure and are more extensible. Currently, most keywords do not have a maintainer. More maintainers will be added as more people volunteer to be maintainers. This patch also updates the CONTRIBUTING.md file to point to this file instead of listing the keywords separately. When this file is committed the wiki will also be updated accordingly. Change-Id: Ib0abfeb39a3ca01b74b340e24dc9a2cd95ff813f Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/2760 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-04-21tests: Remove unused options from tests.pyAndreas Sandberg
The test sub-command in tests.py incorrectly accepts various formatting options in its usage string. These options aren't needed since the test command doesn't produce any output. Change-Id: I6d4731aa32a25a2286aa66548eaa0154a9392f79 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2840 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-18x86: fixed branching() computation for branch uopsSanti Galan
When a branch micro-op belongs to a flow and the micro-op does not change the nPC and just updates the nuPC (like a 'rep movs' flow), branching() function always returns not-taken no matter actual micro-branch outcome. Provided fix adds to the equation nuPC attribute checking since these kind of branch micro-op only updates that pointer. This issue has been found while debugging the performance of a copy-loop implemented with memcopy function. Without the fix, 'rep movss' internal micro-branch was always predicted as not-taken causing an squash event after every branch micro-branch execution. Using the provided test, branch mispredition went from 1922 without the fix to 7. Change-Id: I1bcbefae26aef47e3135817ef99b53d0ea0a98fa
2017-04-14scons: When spawning the linker process, don't involve the shell.Gabe Black
The command line can be too long, causing bash to choke. This means we can't use any shell syntax like shell variables or redirection when linking, but that should be easy to avoid. Change-Id: Ie6c8ecab337cef6bd3c7e403346ced06f46f0993 Reviewed-on: https://gem5-review.googlesource.com/2780 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Steve Reinhardt <stever@gmail.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-11config, arm: Add an example power modelAndreas Sandberg
Add a script to demonstrate how power models can be wired to gem5 models. The script is meant as an example only and does not correlate with any realistic implementation. Change-Id: Ib95a74b2cb4af77a7816e3e8e89c89f3460775a1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2721 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-11power: Allow global stats in power equationsStephan Diestelhorst
Allow global stats such as sim_seconds in power equations to make it possible to convert from event stats to rate stats. Change-Id: I429abe0ffadc0dbd162eb39e0897143be472ef65 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2720 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-11misc: minor fix for the gem5-SystemC/TLM coupling.Éder F. Zulian
This patch has a minor fix for the coupling between gem5 and SystemC-TLM. It also fixes some typos in the related documentation. Change-Id: I894568729b8ebdacc5b81c9f46e8f9d137da210f Reviewed-on: https://gem5-review.googlesource.com/2480 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-11riscv: Fix crashes with large or frequent mmapsAlec Roelke
This patch fixes a bug where increasing the mmap region too much causes it to run into already-allocated memory, which causes gem5 to fail an assertion. Previously, the stack was incorrectly set up such that the end of the mmap region and the top of the stack were the same address and both would grow downward. With this patch, the top of the stack has been separated from the end of mmap and moved up, and the mmap region now grows upward instead of downward. [Rebase to master branch and remove dependencies.] Change-Id: I7271ff478fff2994f918bc5003a6139b9ba6a520 Reviewed-on: https://gem5-review.googlesource.com/2680 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-08power: Clarify the unit used for the power equations (W)Stephan Diestelhorst
Change-Id: Iab5070fc9b666fcb5b49b0e2b99a4a1605b3b721 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2017-04-06power: Add a voltage variable to power expressionsAndreas Sandberg
There is currently no good way of extracting the current operating voltage in MathExprPowerModels. This change adds a magic variable, 'voltage', that can be referenced from such expressions to get the current operating voltage. Change-Id: Ice3c9a4a221921a542de5da52f83f3f88862d246 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2662 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-06power: Add error checking to MathExprPowerModelAndreas Sandberg
MathExprPower model currently doesn't print any useful error messages if an expression fails to evaluate. To add insult to injury, the model only detects a failure when dumping stats and not at initialization. This change adds a verification step in startup() that ensures that all of the referenced stats actually exist. Change-Id: I8f71c73341578d5882c8d93e482f5383fbda5f1d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2661 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-05ruby: Fix MOESI_CMP_directory for new DMA status changes.Javier Cano-Cano
Multiple outstanding DMA requests introduced new DMA states that didn't be considered into slicc code. This patch implements the missed DMA state changes on MOESI_CMP_directory protocol. Change-Id: I700d441d76556b7e77e0d507904af6ec6ba59cc2 Signed-off-by: Michael LeBeane <michael.lebeane@amd.com> Reviewed-on: https://gem5-review.googlesource.com/2380 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: fix Linux problems with LR and SC opsAlec Roelke
Some of the functions in the Linux toolchain that allocate memory make use of paired LR and SC instructions, which didn't work properly for that toolchain. This patch fixes that so attempting to use those functions doesn't cause an endless loop of failed SC instructions. Change-Id: If27696323dd6229a0277818e3744fbdf7180fca7 Reviewed-on: https://gem5-review.googlesource.com/2340 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: fix compatibility with Linux toolchainAlec Roelke
Previously, RISC-V in gem5 only supported RISC-V's Newlib toolchain (riscv64-unknown-elf-*) due to incorrect assumptions made in the initial setup of the user stack in SE mode. This patch fixes that by referring to the RISC-V proxy kernel code (https://github.com/riscv/riscv-pk) and setting up the stack according to how it does it. Now binaries compiled using the Linux toolchain (riscv64-unknown-linux-gnu-*) will run as well. [Update for recent changes to MemState to add accessors and mutators to get its members.] Change-Id: I6d2c486df7688efe3df54273e9aa0fd686851285 Reviewed-on: https://gem5-review.googlesource.com/2305 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: add remote gdb supportAlec Roelke
This patch adds support for debugging with remote GDB to RISC-V. Using GDB compiled with the RISC-V GNU toolchain, it is possible to pause and continue execution, view debugging information, etc. As with the rest of RISC-V, this does not support full-system mode. Change-Id: I2d3a8be614725e1be4b4c283f9fb678a0a30578d Reviewed-on: https://gem5-review.googlesource.com/2304 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: fix error on memory op address overflowAlec Roelke
Previously, if a memory operation referenced an address that caused the data to wrap around to the beginning of the memory (such as -1 or 0xFFFFFFFFFFFFFFFF), an assert would fail during address translation and gem5 would crash. This patch fixes that by checking for such a case in RISC-V's TLB code and returning a fault from translateData if that would happen. Because RISC-V does support unaligned memory accesses, no checking is performed to make sure that an access doesn't cross a cache line. [Update creation of page table fault to use make_shared.] [Add comment explaining the change and assertion that the memory request isn't zero size.] Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410 Reviewed-on: https://gem5-review.googlesource.com/2345 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05riscv: enable unaligned memory accessesAlec Roelke
Sometimes an ld instruction will be split across a cache boundary. Previously RISC-V was set to not allow this. This patch fixes that. Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f Reviewed-on: https://gem5-review.googlesource.com/2341 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update some stats after simulated program exit behavior was changed.Gabe Black
The following CL delayed program exit and changed the stats for many if not most of the SE mode regressions. commit 2c1286865fc2542a0586ca4ff40b00765d17b348 Author: Brandon Potter <Brandon.Potter@amd.com> Date: Wed Mar 1 14:52:23 2017 -0600 syscall-emul: Rewrite system call exit code Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16 Reviewed-on: https://gem5-review.googlesource.com/2656 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update the stats for 70.twolf for x86 o3-timing mode.Gabe Black
The following CL changed the stats: commit 43418e7f81099072fb7d56dae11110ae1d858162 Author: Brandon Potter <Brandon.Potter@amd.com> Date: Wed Mar 1 13:07:43 2017 -0600 syscall-emul: Move memState into its own file It would be a good idea to try to figure out why, since it doesn't *look* like this change was intended to move things around in memory or otherwise change simulated behavior. Change-Id: I0173ffdfb680a91b8c91f2bf5d7f72c76e7a8b63 Reviewed-on: https://gem5-review.googlesource.com/2655 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update 04.gpu stats.Gabe Black
A new stat was added by the CL: commit b043dcf58ad766582aeab162fb855cc3fc95f2cf Author: Andreas Sandberg <andreas.sandberg@arm.com> Date: Mon Feb 27 13:17:51 2017 +0000 gpu-compute: Fix Python/C++ object hierarchy discrepancies Change-Id: I665a7eb0bea19f379c5fbaaf4686fcbe8c008159 Reviewed-on: https://gem5-review.googlesource.com/2654 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update ARM FS stats.Gabe Black
The change below changed the behavior of interrupts on ARM and changed the stats for the 10.linux-boot regression. commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b Author: Sudhanshu Jha <sudhanshu.jha@arm.com> Date: Mon Feb 27 10:29:56 2017 +0000 arm, kmi: Clear interrupts in KMI devices Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a Reviewed-on: https://gem5-review.googlesource.com/2653 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update the 40.m5threads stats.Gabe Black
The change below changed the stats for the o3 version of the 40.m5threads regression. commit 2367198921765848a4f5b3d020a7cc5776209f80 Author: Brandon Potter <brandon.potter@amd.com> Date: Mon Feb 27 14:10:15 2017 -0500 syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations Change-Id: I601c58d8d1453cf93f2065ea5816b63b553610e0 Reviewed-on: https://gem5-review.googlesource.com/2652 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Rename num_syscalls to numSyscalls in the reference stats.Gabe Black
The name of the stat was changed in the following change which broke all the reference outputs. commit 2367198921765848a4f5b3d020a7cc5776209f80 Author: Brandon Potter <brandon.potter@amd.com> Date: Mon Feb 27 14:10:15 2017 -0500 syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations Change-Id: Id98b085ccae098c50c434ad81a72beee46084f40 Reviewed-on: https://gem5-review.googlesource.com/2651 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update 01.hello-2T-smt and 40.perlbmks stats on ARM/Alpha o3-timing.Gabe Black
The following change removed a write to an integer register when completing a system call. This changed the reference statistics slightly. commit 073cb266079edddec64ea8cd5169dd2cbef8f812 Author: Brandon Potter <brandon.potter@amd.com> Date: Mon Feb 27 14:10:02 2017 -0500 syscall_emul: [patch 14/22] adds identifier system calls Change-Id: I3bee42ab826dd9cbc49aab34340da57caf4f045d Reviewed-on: https://gem5-review.googlesource.com/2650 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update the stats for 04.gpu for x86/linux/gpu-ruby-GPU_Rf0.Gabe Black
These stats were changed by this CL: commit a4b546c3a139aeb33f087422637ac06fc4477d11 Author: Matthew Poremba <matthew.poremba@amd.com> Date: Thu Jan 19 11:58:59 2017 -0500 ruby: Add occupancy stats to MessageBuffers Change-Id: I9713ed44d94cba424cdfa92d746dfe8007583b40 Reviewed-on: https://gem5-review.googlesource.com/2649 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update the solaris boot stats for the new op classes.Gabe Black
The change below introduced some new op classes which have their own stats, and the counts the instructions used to be under have gone down. commit 6c72c3551978ef2eabbe9727bf24fd2fcf385318 Author: Fernando Endo <fernando.endo2@gmail.com> Date: Sat Oct 15 14:58:45 2016 -0500 cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass Change-Id: Ifa3a279493f503585a7b2cbb2785b106e24184bb Reviewed-on: https://gem5-review.googlesource.com/2648 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update the solaris boot stats for the default snoop_filter.Gabe Black
The snoop_filter was enabled by default by this change: commit 080d4e08d627b5b726afec71d38370373b7376c5 Author: Andreas Hansson <andreas.hansson@arm.com> Date: Fri Aug 12 14:11:45 2016 +0100 mem: Add snoop filter to SystemXBar by default Change-Id: I850473c70437588b47812f1dc00d6ecdb66daa36 Reviewed-on: https://gem5-review.googlesource.com/2647 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update the solaris boot stats for new snoopTraffic stat.Gabe Black
The following change added the new stat: commit 0020662459fdd9efcfe9864ef12160515434ccdb Author: David Guillen Fandos <david.guillen@arm.com> Date: Thu Jul 21 17:19:14 2016 +0100 mem: Add snoop traffic statistic Change-Id: I9ee0fb4b8cc97c6b94e76ab5524f89c78c97d1a6 Reviewed-on: https://gem5-review.googlesource.com/2646 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05config: Add a default system disk image for SPARC FS.Gabe Black
When the change below removed the hard coded disk name for the SPARC FS configuration, it broke the regression which had not specified a disk name. This change adds a default disk name so that the regression will continue to work like it used to, but preserving the effect of this other change. commit 86a25bbcee88f6e69299867b6264885d738f636e Author: Jakub Jermar <jakub@jermar.eu> Date: Tue Jul 19 09:52:46 2016 -0500 config: Allow SPARC FS image to be specified on the command line Change-Id: Ieb317b2bf573a4f2fc435d34cccd1f246c28d84c Reviewed-on: https://gem5-review.googlesource.com/2645 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Update SPARC solaris boot stats.Gabe Black
The CPU power state bins where changed by the following CL: commit fb5fc11da49938660ea22c336964677cdba890e1 Author: David Guillen Fandos <david.guillen@arm.com> Date: Mon Jun 6 17:16:43 2016 +0100 pwr: Low-power idle power state for idle CPUs Change-Id: I8b3924681c8a85b7bbe061b671faf274ce882f91 Reviewed-on: https://gem5-review.googlesource.com/2644 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Remove stats from the SPARC solaris boot which were silenced.Gabe Black
These were silenced in: commit d4342aff4ce347ad8ab5a01fdd41993106cd3ece Author: Andreas Sandberg <andreas.sandberg@arm.com> Date: Mon Jun 6 17:16:43 2016 +0100 stats: Silence unused power stats Change-Id: I273e8190b76335505bedfea88ef89abee1739b8a Reviewed-on: https://gem5-review.googlesource.com/2643 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Add a boat load of stats to the SPARC solaris boot regression.Gabe Black
A large number of stats were added by the following change: commit 5350879f499470a2683dfec6cff021dd7ac20fa6 Author: David Guillen Fandos <david.guillen@arm.com> Date: Mon Jun 6 17:16:43 2016 +0100 pwr: Add power states to ClockedObject Change-Id: Iec32bb7f701db0a09be26fe5ffb2812385f972c2 Reviewed-on: https://gem5-review.googlesource.com/2642 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-05stats: Un-empty the SPARC FS stats.txt file.Gabe Black
This was emptied accidentally by the CL below. A lot of other files were too, but those were eventually refilled. commit 62b6ff22ec1f90014b1d0fc778014bdb38cc09ce Author: Curtis Dunham <Curtis.Dunham@arm.com> Date: Tue May 31 11:07:18 2016 +0100 stats: update for snoop filter tweak Change-Id: I34aefca51a92a6a98f6a8fdbdab7106cc1fff171 Reviewed-on: https://gem5-review.googlesource.com/2641 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-04-05scons: Fix hook installation error caused by stale cacheAndreas Sandberg
Due to the way SCons caches some file system state internally, it sometimes "remembers" that a file or directory didn't exist at some point. The git hook installation script sometimes needs to create a hooks directory in the repository. Due to the cached state of the hooks directory, the build system tries to create it twice. The second mkdir operation leads to an error since the directory already exists. Fix this issue by clearing the cached state of the hooks directory after creating it. Change-Id: I3f67f75c06ef928b439a0742f7619b7e92ed093b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2660 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-04-03arm, kvm: implement GIC state transferCurtis Dunham
This also allows checkpointing of a Kvm GIC via the Pl390 model. Change-Id: Ic85d81cfefad630617491b732398f5e6a5f34c0b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2444 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm, dev: add basic support for GICC_BPR registerCurtis Dunham
The Binary Point Register (BPR) specifies which bits belong to the group priority field (which are used for preemption) and which to the subpriority field (which are ignored for preemption). Change-Id: If51e669d23b49047b69b82ab363dd01a936cc93b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2443 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm, dev: refactor GIC Pl390 GICD_ITARGETSRn handlingCurtis Dunham
The aforementioned registers (Interrupt Processor Targets Registers) are banked per-CPU, but are read-only. This patch eliminates the per-CPU storage of these values that are simply computed. Change-Id: I52cafc2f58e87dd54239a71326c01f4923544689 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2442 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm: refactor packet processing in Pl390 GICCurtis Dunham
Change-Id: I696703418506522ba90df5c2c4ca45c95a6efbea Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2441 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm: Don't panic when checking coprocessor read/write permissionsNikos Nikoleris
Instructions that use the coprocessor interface check the current program status to determine whether the current context has the priviledges to read from/write to the coprocessor. Some modes allow the execution of coprocessor instructions, some others do not allow it, while some other modes are unexpected (e.g., executing an AArch32 instruction while being in an AArch64 mode). Previously we would unconditionally trigger a panic if we were in an unexpected mode. This change removes the panic and replaces it with an Undefined Instruction fault that triggers if and when a coprocessor instruction commits in an unexpected mode. This allows speculative coprocessor instructions from unexpected modes to execute but prevents them from gettting committed. Change-Id: If2776d5bae2471cdbaf76d0e1ae655f501bfbf01 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2281 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm: Treat Write-Through Normal memory as Non-CacheableNikos Nikoleris
A completed write to a memory location that is Write-Through Cacheable has to be visible to an external observer without the need of explicit cache maintenance. This change adds support for Write-Through Cacheable Normal memory and treats it as Non-cacheable. This incurs a small penalty as accesses to the memory do not fill in the cache but does not violate the properties of the memory type. Change-Id: Iee17ef9d952a550be9ad660b1e60e9f6c4ef2c2d Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2280 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-03sim: Handle cases where Drainable::resume() creates objectsAndreas Sandberg
There are cases where Drainable objects need to create new objects in Drainable::resume(). In such cases, the local drain state will be inherited from the DrainManager. We currently set the state to Running as soon as we start resuming the simulator. This means that new objects are created in the Running state rather than the Drained state, which the resume code assumes. Depending on the traversal order in DrainManager::resume(), this sometimes triggers a panic because the object being resumed is in the wrong state. This change introduces a new drain state, Resuming, that the DrainManager enters as soon as it starts resuming the simulator. Objects that are created while resuming are created in this state. Such objects are then resumed in a subsequent pass over the list of Drainable objects that need to be resumed. Once all objects have been resumed, the simulator enters the Running state. Change-Id: Ieee8645351ffbdec477e9cd2ff86fc795e459617 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2600 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03config, arm: Add multi-core KVM support to bL configAndreas Sandberg
Add support for KVM in the big.LITTLE(tm) example configuration. This replaces the --atomic option with a --cpu-type option that can be used to switch between atomic, kvm, and timing simulation. When running in KVM mode, the simulation script automatically assigns separate event queues (threads) to each of the simulated CPUs. All simulated devices, including CPU child devices (e.g., interrupt controllers and caches), are assigned to event queue 0. Change-Id: Ic9a3f564db91f5a3d3cb754c5a02fdd5c17d5fdf Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2561 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03config, arm: Unify checkpoint path handling in bL configsAndreas Sandberg
The vanilla bL configuration file and the dist-gem5 configuration file use slightly different code paths when restoring from checkpoints. Unify this by passing the parsed options to the instantiate() method and adding an optional checkpoint keyword argument for checkpoint directories (only used by the dist-gem5 script). Change-Id: I9943ec10bd7a256465e29c8de571142ec3fbaa0e Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2560 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03arm, kvm: Override the kernel's default MPIDR valueAndreas Sandberg
The kernel and gem5 derive MPIDR values from CPU IDs in slightly different ways. This means that guests running in a multi-CPU setup sometimes fail to bring up secondary CPUs. Fix this by overriding the MPIDR value in virtual CPUs just after they have been instantiated. Change-Id: I916d44978a9c855ab89c80a083af45b0cea6edac Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2461 Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03dev, arm: Fix multi-core KVM race in the generic timerAndreas Sandberg
The generic timer sometimes needs to access global state. This can lead to race conditions when simulating a multi-core KVM system where each core lives in its own thread. In that case, the setMiscReg and readMiscReg methods are called from the thread owning the CPU and not the global device thread. Change-Id: Ie3e982258648c8562cce0b30a0c122dfbfaf42cd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2460 Reviewed-by: Weiping Liao <weipingliao@google.com>
2017-04-03dev: Align BAR0 size to power of 2 for VirtIO devicesSascha Bischoff
When setting the size of a PCI BAR, the kernel only supports powers of two (as per the PCI spec). Previously, the size was incorrectly read by the kernel, and the address ranges assigned to the PCI devices could overlap, resulting in gem5 crashes. We now round up to the next power of two. Kudos to Sergei Trofimov who helped to debug this issue! Change-Id: I54ca399b62ea07c09d4cd989b17dfa670e841bbe Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-by: Sergei Trofimov <sergei.trofimov@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2580 Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
2017-04-03dev: Add a dummy VirtIO deviceAndreas Sandberg
VirtIO transport interfaces always expect a VirtIO device pointer. However, there are cases (in particular when using VirtIO's MMIO interface) where we want to instantiate an interface without a device. Add a dummy device using VirtIO device ID 0 and no queues to handle this use case. Change-Id: I6cbe12fd403903ef585be40279c3b1321fde48ff Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2325 Reviewed-by: Weiping Liao <weipingliao@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-04-03dev: Rename VirtIO PCI debug flagAndreas Sandberg
Rename VIOPci -> VIOIface to avoid having a separate flag for the MMIO interface. Change-Id: I99f9210fa36ce33662c48537fd3992cd9a69d349 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2324 Reviewed-by: Weiping Liao <weipingliao@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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