Age | Commit message (Collapse) | Author |
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and resulting recursive import trickiness.
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Some tweaking to deal with mutually recursive imports.
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rename : src/python/m5/config.py => src/python/m5/SimObject.py
extra : convert_revision : 166f7bfabfd20100e93d26a89382469465859988
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Import of changes for auto-generation of C++ param structs
from my old m5 working directory.
This code is *broken* because pieces need to be shuffled around
to satisfy name dependencies, but that really messes up the
diff, so I want to make an intermediate commit here.
src/python/m5/config.py:
Import of changes for auto-generation of C++ param structs
from my old m5 working directory.
This code is *broken* because pieces need to be shuffled around
to satisfy name dependencies, but that really messes up the
diff, so I want to make an intermediate commit here.
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Clean up help output.
util/regress:
Clean up help output.
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into vm1.(none):/home/stever/bk/newmem-head
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to make it more usable by regular folks.
util/regress:
Get rid of extra stuff only needed by cron job,
to make it more usable by regular folks.
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extra : convert_revision : e113c05af5eec846db526d734cce8ff66aa95d72
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build_opts/ALPHA_SE:
Add O3CPU to default CPU model list.
tests/SConscript:
Add o3-timing configuration.
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Don't consider it a success if no stats at all were found.
tests/diff-out:
Don't consider it a success if no stats at all were found.
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extra : convert_revision : 733f10abdf17d1f7eeca912f84f3df37e56fe510
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
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throughout CPU models
src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA
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allowing derived classes to be simplified.
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configs/example/se.py:
Add missing cpu mem param.
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Verify that BAR sizes are powers of two.
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tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt:
tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout:
Update reference outputs
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the framework. Doesn't work, but also doesn't break uni-processor systems.
Working on pulling out the changes in the cache so that it remains working.
src/mem/bus.cc:
Changes for multi-phase snoop
Some code for registering snoop ranges (a version that compiles and runs, but does nothing)
src/mem/bus.hh:
Changes for multi-phase snoop
src/mem/packet.hh:
Flag for multi-phase snoop
src/mem/port.hh:
Status for multi-phase snoop
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extra : convert_revision : 4c2e5263bba16e3bcf03aabe36ff45ec36de4720
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into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem
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into ewok.(none):/home/gblack/m5/newmem
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Add checks for swig & libz, version check for swig.
Factor out version check code into function, use for mysql too.
SConstruct:
Add checks for swig & libz, version check for swig.
Factor out version check code into function, use for mysql too.
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into ewok.(none):/home/gblack/m5/newmem
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Added in the filename parameter which is provided for the user space linker.
Fix the ordering and alignment of stack elements.
Made mmap start with the address it has been seen starting with "in the wild"
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returning the size of a pointer to an IntReg
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1. alignaddr wrote it's address to a floating point register rather than a gpr.
2. sethi was sign extending it's immediate value.
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into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem
src/python/m5/objects/BaseCPU.py:
Merge duplicate change
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src/mem/packet.hh:
Make sure packets set the time parameter correctly.
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Add temporary cpu.mem parameter settings.
configs/example/fs.py:
Add temporary cpu.mem parameter settings.
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rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini => tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out => tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout
rename : tests/test-progs/hello/bin/alpha/linux/hello => tests/test-progs/hello/bin/alpha/tru64/hello
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Arg to m5.simulate() is a delta, not an absolute curTick value.
I didn't test this change, but I'm not convinced the previous
example was tested either, so I don't feel too badly about it.
configs/example/fs.py:
Arg to m5.simulate() is a delta, not an absolute curTick value.
I didn't test this change, but I'm not convinced the previous
example was tested either, so I don't feel too badly about it.
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extra : convert_revision : ef7df7b83b3e2b5da02408c674169ccbed75a441
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Fix BATCH_CMD bug.
tests/SConscript:
Fix BATCH_CMD bug.
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