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AgeCommit message (Expand)Author
2013-01-07mem: Add sanity check to packet queue sizeAndreas Hansson
2013-01-07ruby: Fix missing cxx_header in SwitchAndreas Hansson
2013-01-07scons: Fix libelf linking errors when using clang/llvmAndreas Hansson
2013-01-07config: Replace second keyboard with a mouse.Chris Emmons
2013-01-07mem: Fix a bug in the memory serialization file namingAndreas Hansson
2013-01-07arm: Make ID registers ISA parametersAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2013-01-07o3: Fix issue with LLSC ordering and speculationAli Saidi
2013-01-07cpu: rename the misleading inSyscall to noSquashFromTCAli Saidi
2013-01-07tests: Always specify memory mode in every test system.Ali Saidi
2013-01-07tests: Create base classes to encapsulate common test configurationsAndreas Sandberg
2013-01-07cache: add note about where conflicts are handledAli Saidi
2013-01-04regressions: stats update due to decoder changesNilay Vaish
2013-01-04Decoder: Remove the thread context get/set from the decoder.Gabe Black
2013-01-04X86: Move address based decode caching in front of the predecoder.Gabe Black
2013-01-04SPARC: Keep a copy of the current ASI in the decoder.Gabe Black
2013-01-04ARM: Keep a copy of the fpscr len and stride fields in the decoder.Gabe Black
2012-12-30x86 regressions: stats update due to new x87 instructionsNilay Vaish
2012-12-30x86: implement x87 fp instruction fnstswNilay Vaish
2012-12-30x86: implement x87 fp instruction fsincosNilay Vaish
2012-12-12arm regressions: updates to config.ini, terminal filesNilay Vaish
2012-12-12arm: set uopSet_uop as conditional or unconditional controlNathanael Premillieu
2012-12-12arm: set movret_uop as conditional or unconditional controlNathanael Premillieu
2012-12-11regressions: stats update due to stats from ruby prefetcherNilay Vaish
2012-12-11ruby: add support for prefetching to MESI protocolNilay Vaish
2012-12-11ruby: modify the directed tester to read/write streamsNilay Vaish
2012-12-11ruby: change slicc to allow for constructor argsNilay Vaish
2012-12-11ruby: add a prefetcherNilay Vaish
2012-12-11ruby: add functions for computing next stride/page addressNilay Vaish
2012-12-06regression test: update a couple of config.ini filesNilay Vaish
2012-12-06TournamentBP: Fix some bugs with table sizes and countersErik Tomusk
2012-12-06inorder cpu: add missing DPRINTF argumentMalek Musleh
2012-12-06o3 cpu: remove some unused buggy functions in the lsqNathanael Premillieu
2012-11-19config: Fix description of checkpoint option from cycle to tickAndreas Hansson
2012-11-16sim: have a curTick per eventqNilay Vaish
2012-11-10regressions: stats update due to ruby functional access patchNilay Vaish
2012-11-10ruby: support functional accesses in garnet flexible networkNilay Vaish
2012-11-10ruby: bug in functionalRead, revert recent changesNilay Vaish
2012-11-08mem: Fix DRAM draining to ensure write queue is emptyAndreas Hansson
2012-11-03x86, util: add m5_writefile to m5op_x86.SLluis Vilanova
2012-11-02ruby: reset and dump stats along with reset of the systemHamid Reza Khaleghzadeh ext:(%2C%20Lluc%20Alvarez%20%3Clluc.alvarez%40bsc.es%3E%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2012-11-02mem: fix use after free issue in memories until 4-phase work complete.Ali Saidi
2012-11-02update stats for preceeding changesAli Saidi
2012-11-02mem: Add support for writing back and flushing cachesAndreas Sandberg
2012-11-02sim: Add drain methods to request additional cleanup operationsAndreas Sandberg
2012-11-02sim: Add SWIG interface for SerializableAndreas Sandberg
2012-11-02python: Rename doDrain()->drain() and make it do the right thingAndreas Sandberg
2012-11-02sim: Reuse the code to change memory mode.Andreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02cpu: O3 add a header declaring the DerivO3CPUAndreas Sandberg