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AgeCommit message (Expand)Author
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-10-15Stats: Update memtest stats after setting clockAndreas Hansson
2012-10-15Configs: Set the memtest clock to a reasonable valueAndreas Hansson
2012-10-15Stats: Update stats for new default L1-to-L2 bus clock and widthAndreas Hansson
2012-10-15Regression: Use CPU clock and 32-byte width for L1-L2 busAndreas Hansson
2012-10-15Stats: Update stats for use of two-level builderAndreas Hansson
2012-10-15Regression: Use addTwoLevelCacheHierarchy in configsAndreas Hansson
2012-10-15Clock: Inherit the clock from parent by defaultAndreas Hansson
2012-10-15Param: Fix proxy traversal to support chained proxiesAndreas Hansson
2012-10-15Mem: Use range operations in bus in preparation for stripingAndreas Hansson
2012-10-11Mem: Determine bus block size during initialisationAndreas Hansson
2012-10-11Doxygen: Update the version of the DoxyfileAndreas Hansson
2012-10-02Regression Tests: Update statisticsNilay Vaish
2012-10-02ruby: makes some members non-staticNilay Vaish
2012-10-02ruby: changes to simple networkNilay Vaish
2012-10-02ruby: rename template_hack to templateNilay Vaish
2012-10-02ruby: remove unused code in protocolsNilay Vaish
2012-10-02ruby: remove some unused things in sliccNilay Vaish
2012-10-02ruby: move functional access to ruby systemNilay Vaish
2012-09-30MI coherence protocol: add copyright noticeNilay Vaish
2012-09-28Configs: SE script fix for Alpha and Ruby simulationsMalek Musleh
2012-09-27Configs: Fix memtest cache latency to match new parametersAndreas Hansson
2012-09-27Configs: Fix memtest.py by moving the system portAndreas Hansson
2012-09-25ARM: update stats for bp and squash fixes.Ali Saidi
2012-09-25MEM: Put memory system document into doxygenDjordje Kovacevic
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-25Statistics: Add a function to configure periodic stats dumpingSascha Bischoff
2012-09-25ARM: added support for flattened device tree blobsDam Sunwoo
2012-09-25O3: Pack the comm structures a bit better to reduce their size.Ali Saidi
2012-09-25mem: Add a gasket that allows memory ranges to be re-mapped.Ali Saidi
2012-09-25ARM: Squash outstanding walks when instructions are squashed.Ali Saidi
2012-09-25Util: Added script to semantically diff two config.ini filesSascha Bischoff
2012-09-25arm: Use a static_assert to test that miscRegName[] is completeAndreas Sandberg
2012-09-25base: Check for static_assert support and provide fallbackAndreas Sandberg
2012-09-25sim: Move CPU-specific methods from SimObject to the BaseCPU classAndreas Sandberg
2012-09-25sim: Remove SimObject::setMemoryModeAndreas Sandberg
2012-09-25CPU: Add abandoned instructions to O3 Pipe ViewerDjordje Kovacevic
2012-09-25ARM: Inst writing to cntrlReg registers not set as control instNathanael Premillieu
2012-09-25ARM: Predict target of more instructions that modify PC.Ali Saidi
2012-09-25gem5: Update the README file to be a bit less out-of-date.Ali Saidi
2012-09-25build: Add missing dependencies when building param SWIG interfacesAndreas Sandberg
2012-09-24Stats: Update stats for twosys-tsunami after setting CPU clockAndreas Hansson
2012-09-24Regression: Set the clock for twosys-tsunami CPUsAndreas Hansson
2012-09-23RubyPort and Sequencer: Fix drainingJoel Hestness
2012-09-21SimpleDRAM: A basic SimpleDRAM regressionAndreas Hansson
2012-09-21DRAM: Introduce SimpleDRAM to capture a high-level controllerAndreas Hansson
2012-09-21TrafficGen: Add a basic traffic generator regressionAndreas Hansson
2012-09-21TrafficGen: Add a basic traffic generatorAndreas Hansson
2012-09-21Mem: Tidy up bus member variables typesAndreas Hansson
2012-09-21Scons: Verbose messages when dependencies are not installedAndreas Hansson