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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
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Age
Commit message (
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Author
2012-06-29
Cache: Only invalidate a line in the cache when an uncacheable write is seen.
Ali Saidi
2012-06-29
ARM: Update version of linux we claim to be to 3.0.0.
Ali Saidi
2012-06-29
ARM: Fix issue with predicted next pc being wrong because of advance() ordering.
Ali Saidi
2012-06-27
ARM: Fix address range issue with VExpress EMM
Ali Saidi
2012-06-20
swig: Use SWIG from environment when determining version
Andreas Hansson
2012-06-18
Build: Point to the appropriate tcmalloc package
Andreas Hansson
2012-06-11
configs: add run scripts for ics/gb versions of android and bbench
Anthony Gutierrez
2012-06-11
ARM: implement the ProcessInfo methods
Anthony Gutierrez
2012-06-11
scons: Make compiler version error more verbose and easier to debug.
Ali Saidi
2012-06-11
Regression: Fix some bugs in simple-timing-mp-ruby.py.
Marc Orr
2012-06-08
Timing CPU: Remove a redundant port pointer
Andreas Hansson
2012-06-08
Power: Fix MaxMiscDestRegs which was set to zero
Andreas Hansson
2012-06-07
X86 TLB: Add a missing = sign
Nilay Vaish
2012-06-07
mem: Delay deleting of incoming packets by one call.
Ali Saidi
2012-06-07
X86 TLB: Fix for gcc 4.4.3
Jayneel Gandhi
2012-06-07
Config: call to setWorkCountOptions() for all ISAs
Nilay Vaish
2012-06-07
Config: Remove setMipsOptions
Nilay Vaish
2012-06-07
Config: changes to a couple of error msgs
Nilay Vaish
2012-06-05
cpu: Don't init simple and inorder CPUs if they are defered.
Anthony Gutierrez
2012-06-05
ISA: Back-out NoopMachInst as a StaticInstPtr change.
Ali Saidi
2012-06-05
cpt: update some comments in the checkpoint migration script
Ali Saidi
2012-06-05
all: Update stats for memory per master and total fix.
Ali Saidi
2012-06-05
stats: when applying an operation to two vectors sum the components first.
William Wang
2012-06-05
Mem: add per-master stats to physmem
Dam Sunwoo
2012-06-05
ARM: Add PCIe support to VExpress_EMM model and remove deprecated ELT
Geoffrey Blake
2012-06-05
ARM: removed extra white space
Chander Sudanthi
2012-06-05
ARM: Fix MPIDR and MIDR register implementation.
Chander Sudanthi
2012-06-05
ARM: PS2 encoding fix
Chander Sudanthi
2012-06-05
sim: Provide a framework for detecting out of data checkpoints and migrating ...
Ali Saidi
2012-06-05
stats: Add stats unittest for total calculations.
Ali Saidi
2012-06-05
O3: Clean up the O3 structures and try to pack them a bit better.
Ali Saidi
2012-06-05
sim: Add support for tcmalloc if it's installed and available.
Ali Saidi
2012-06-05
sim: Remove FastAlloc
Ali Saidi
2012-06-05
ARM: Fix over-eager assert in gic.
Ali Saidi
2012-06-05
stats: Provide a mechanism to get a callback when stats are dumped.
Mitchell Hayenga
2012-06-05
ARM: Fix compilation on ARM after Gabe's change.
Ali Saidi
2012-06-04
ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.
Gabe Black
2012-06-04
X86: Update stats for the CPUID change.
Gabe Black
2012-06-04
X86: Ensure that the CPUID instruction always writes its outputs.
Gabe Black
2012-06-04
X86: Ensure that the decoder's internal ExtMachInst is completely initialized.
Gabe Black
2012-05-31
Bus: Split the bus into a non-coherent and coherent bus
Andreas Hansson
2012-05-09
Stats: Fix stats to match output after changeset 8800b05e1cb3
Andreas Hansson
2012-05-30
gcc: Small fixes to compile with gcc 4.7
Andreas Hansson
2012-05-30
Bus: Remove redundant packet parameter from isOccupied
Andreas Hansson
2012-05-30
Bus: Turn the PortId into a transport function parameter
Andreas Hansson
2012-05-30
Packet: Unify the use of PortID in packet and port
Andreas Hansson
2012-05-30
Packet: Updated comments for src and dest fields
Andreas Hansson
2012-05-30
Bridge: Split deferred request, response and sender state
Andreas Hansson
2012-05-28
X86: Use the HandyM5Reg to avoid a register read and some logic in the TLB.
Gabe Black
2012-05-27
X86: Add a 32 bit hello world test binary.
Gabe Black
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