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2009-05-13stats: tidy up the Distribution type a little bitNathan Binkert
2009-05-13stats: fancy is a bad nameNathan Binkert
2009-05-13stats: clean up the code for printing statsNathan Binkert
2009-05-13mips-merge: merge hello world regress for inorder cpuKorey Sewell
w/latest changes
2009-05-13inorder-regress: add hello MIPS_SEKorey Sewell
2009-05-12ruby: deal with printf warnings and convert some to cprintfNathan Binkert
2009-05-12ruby: remove random uint typedef and use unsignedNathan Binkert
2009-05-12ruby: Make ruby's Map use hashmap.hh to simplify things.Nathan Binkert
2009-05-12gcc: work around a bogus gcc errorNathan Binkert
2009-05-12slicc: work around improper initialization of a global in slicc.Nathan Binkert
2009-05-12slicc: clean up the slicc environment so things build properly on mac.Nathan Binkert
2009-05-13mips_se: add cpu_models to build optionsKorey Sewell
2009-05-13inorder-mips: Remove eaComp & memAcc; use 'visible' eaCompKorey Sewell
Inorder expects eaComp to be visible through StaticInst object. This mirrors a similar change to ALPHA... Needs to be done for SPARC and whatever other ISAs want to use InOrderCPU
2009-05-13arch-mips: add regWidth constant to float regfileKorey Sewell
2009-05-12cpus: add InOrderCPU to default buildKorey Sewell
regressions need this so they build the model
2009-05-12inorder-regress: missing regress config fileKorey Sewell
regressions need to access this file to setup the InOrderCPU object
2009-05-12alpha-isa: add mt.hh so it can compile with inorderKorey Sewell
2009-05-12inorder-regress: add vortex ALPHA_SEKorey Sewell
2009-05-12inorder-regress: add twolf ALPHA-SEKorey Sewell
2009-05-12inorder-regress: add hello worldKorey Sewell
2009-05-12inorder-resources: delete eventsKorey Sewell
make sure unrecognized events in the resource pool are deleted and also delete resource events in destructor
2009-05-12inorder-tlb-cunit: merge the TLB as implicit to any memory accessKorey Sewell
TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory and the result is checked before it's sent out to memory. * * *
2009-05-12inorder-tlb: squash insts in TLB correctlyKorey Sewell
TLB had a bug where if it was stalled and waiting , it would not squash all instructions older than squashed instruction correctly * * *
2009-05-12inorder-faults: ignore unalign translation faults for prefetchesKorey Sewell
2009-05-12inorder-stc: update interface to handle store conditionalsKorey Sewell
2009-05-12inorder-float: Fix storage of FP resultsKorey Sewell
inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from the actual floating point register file, the model can figure out what it needs to store
2009-05-12inorder-fetch: update model to use predecoderKorey Sewell
2009-05-12inorder-mem: clean up allocation/deletion of requests/packetsKorey Sewell
* * *
2009-05-12inorder-mem: skeleton support for prefetch/writehintsKorey Sewell
2009-05-12inorder-o3: allow both to compile togetherKorey Sewell
allow InOrder and O3CPU to be compiled at the same time: need to make branch prediction filed shared by both models
2009-05-12inorder-unified-tlb: use unified TLB instead of old TLB modelKorey Sewell
2009-05-12inorder-miscregs: Fix indexing for misc. reg operands and update ↵Korey Sewell
result-types for better tracing of these types of values
2009-05-12inorder/alpha-isa: create eaComp object visible to StaticInst through ISAKorey Sewell
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access * * *
2009-05-12inorder-bpred: edits to handle non-delay-slot ISAsKorey Sewell
Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline
2009-05-12inorder-alpha-port: initial inorder support of ALPHAKorey Sewell
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions * * * Remove namespace from header file. Causes compiler issues that are hard to find * * * Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time * * * Expose memory access size and flags through instruction object (temporarily memAccSize and memFlags to get TLB stuff working.)
2009-05-12isa-parser: made a few changes, but not author-worthyKorey Sewell
2009-05-11Merge Ruby StuffKorey Sewell
2009-05-11ruby: assert(false) should be panic.Nathan Binkert
This also fixes some compiler warnings
2009-05-11stats: remove a few compat leftoversNathan Binkert
2009-05-11python: pull out common code from main that processes argumentsNathan Binkert
2009-05-11stats: forgot an include for the mysql stuffNathan Binkert
2009-05-11scons: add include guards to info.hhNathan Binkert
2009-05-11ruby: add RUBY sticky option that must be set to add ruby to the buildNathan Binkert
Default is false
2009-05-11ruby: Initial references for ruby regressionsSteve Reinhardt
2009-05-11ruby: Set up Ruby regression tests.Steve Reinhardt
2009-05-11ruby: Working M5 interface and updated Ruby interface.Daniel Sanchez
This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu> RubyMemory is now both a driver for Ruby and a port for M5. Changed makeRequest/hitCallback interface. Brought packets (superficially) into the sequencer. Modified tester infrastructure to be packet based. and Ruby can be used together through the example ruby_se.py script. SPARC parallel applications work, and the timing *seems* right from combined M5/Ruby debug traces. To run, % build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t
2009-05-11ruby: Check stderr and not stdin before hanging on an assert.Steve Reinhardt
2009-05-11ruby: decommission codePolina Dudnik
1. Set.* and BigSet.* are replaced with OptBigSet.* which was renamed Set.* 2. Decomissioned all bloom filters 3. Decomissioned ruby/simics directory
2009-05-11ruby: removed dead functions from the sequencerDerek Hower
2009-05-11ruby: Removed g_SIMULATING flagPolina Dudnik
1. removed checks from tester files 2. removed else clause in Sequencer and DirectoryMemory else clause is needed by the tester, it is up to Derek to revive it elsewhere when he gets to it Also: 1. Changed m_entries in DirectoryMemory to a map 2. And replaced SIMICS_read_physical_memory with a call to now-dummy Derek's-to-be readPhysMem function