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2014-10-16misc: Move AddrRangeList from port.hh to addr_range.hhAndreas Hansson
The new location seems like a better fit. The iterator typedefs are removed in favour of using C++11 auto.
2014-10-16ext: Update fputils to rev 6a47fd8358Andreas Sandberg
This patch updates fputils to the latest revision (6a47fd8358) from the upstream repository (github.com/andysan/fputils). Most notably, this includes changes that export a limited set of 64-bit float manipulation and avoids a warning about unused 64-bit floats in clang.
2014-10-16dev: refactor pci config space for sysfs scanningGeoffrey Blake
Sysfs on ubuntu scrapes the entire PCI config space when it discovers a device using 4 byte accesses. This was not supported by our devices, in particular the NIC that implemented the extended PCI config space. This change allows the extended PCI config space to be accessed by sysfs properly.
2014-10-16mem: Add ExternalMaster and ExternalSlave portsAndrew Bardsley
This patch adds two MemoryObject's: ExternalMaster and ExternalSlave. Each object has a single port which can be bound to an externally- provided bridge to a port of another simulation system at initialisation.
2014-10-16sim: SystemC hostingAndrew Bardsley
This patch hosts gem5 onto SystemC scheduler. There's already an upstream review board patch that does something similar but this patch ...: 1) is less obtrusive to the existing gem5 code organisation. It's divided into the 'generic' preparatory patches (already submitted) and this patch which affects no existing files 2) does not try to exactly track the gem5 event queue with notifys into SystemC and so doesn't requive the event queue to be modified for anything other than 'out of event queue' scheduling events 3) supports debug logging with SC_REPORT The patch consists of the files: util/systemc/ sc_gem5_control.{cc,hh} -- top level objects to use to instantiate gem5 Systems within larger SystemC test harnesses as sc_module objects sc_logger.{cc,hh} -- logging support sc_module.{cc,hh} -- a separated event loop specific to SystemC stats.{cc,hh} -- example Stats handling for the sample top level main.{cc,hh} -- a sample top level On the downside this patch is only currently functional with C++ configuration at the top level. The above sc_... files are indended to be compiled alongside gem5 (as a library, see main.cc for a command line and util/systemc/README for more details.) The top-level system instantiation in sc_gem5_control.{cc,hh} provides two classes: Gem5Control and Gem5System Gem5Control is a simulation control class (from which a singleton object should be created) derived from Gem5SystemC::Module which carries the top level simulation control interface for gem5. This includes hosting a system-building configuration file and instantiating the Root object from that file. Gem5System is a base class for instantiating renamed gem5 Systems from the config file hosted by the Gem5Control object. In use, a SystemC module class should be made which represents the desired, instantiable gem5 System. That class's instances should create a Gem5System during their construction, set the parameters of that system and then call instantiate to build that system. If this is all carried out in the sc_core::sc_module-derived classes constructor, the System's external ports will become children of that module and can then be recovered by name using sc_core:: sc_find_object. It is intended that this interface is used with dlopen. To that end, the header file sc_gem5_control.hh includes no other header files from gem5 (and so can be easily copied into another project). The classes Gem5System and Gem5Control have all their member functions declared `virtual' so that those functions can be called through the vtable acquired by building the top level Gem5Control using dlsym(..., "makeGem5Control") and `makeSystem' on the Gem5Control.
2014-10-16sim: EventQueue wakeup on events scheduled outside the event loopAndreas Hansson
This patch adds a 'wakeup' member function to EventQueue which should be called on an event queue whenever an event is scheduled on the event queue from outside code within the call tree of the gem5 event loop. This clearly isn't necessary for normal gem5 EventQueue operation but becomes the minimum necessary interface to allow hosting gem5's event loop onto other schedulers where there may be calls into gem5 from external code which schedules events onto an EventQueue between the current time and the time of the next scheduled event. The use case I have in mind is a SystemC hosting where the event loop is: while (more events) { wait(time_to_next_event or wakeup) setCurTick service events at this time } where the 'wait' needs to be woken up if time_to_next_event becomes shorter due to a scheduled event from SystemC arriving in a gem5 object. Requiring 'wakeup' to be called is a more efficient interface than requiring all gem5 event scheduling actions to affect the host scheduler. This interface could be located elsewhere, say on another global object, or by being passed by the host scheduler to objects which will schedule such events, but it seems cleanest to put it on EventQueue as it is actually a signal to the queue. EventQueue::wakeup is called for async_event events on event queue 0 as it's only important that *some* queue be triggered for such events.
2014-10-16base: Reimplement the DPRINTF mechanism in a Logger classAndrew Bardsley
This patch adds a Logger class encapsulating dprintf. This allows variants of DPRINTF logging to be constructed and substituted in place of the default behaviour. The Logger provides a logMessage(when, name, format, ...) member function like Trace::dprintf and a getOstream member function to use a raw ostream for logging. A class OstreamLogger is provided which generates the customary debugging output with Trace::OstreamLogger::logMessage being the old Trace::dprintf.
2014-10-16arch: Use shared_ptr for all FaultsAndreas Hansson
This patch takes quite a large step in transitioning from the ad-hoc RefCountingPtr to the c++11 shared_ptr by adopting its use for all Faults. There are no changes in behaviour, and the code modifications are mostly just replacing "new" with "make_shared".
2014-10-16o3: Use shared_ptr for MemDepEntryAndreas Hansson
This patch transitions the o3 MemDepEntry from the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no changes in behaviour, and the code modifications are mainly replacing "new" with "make_shared".
2014-10-16mem: Use shared_ptr for Ruby Message classesAndreas Hansson
This patch transitions the Ruby Message and its derived classes from the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no changes in behaviour, and the code modifications are mainly replacing "new" with "make_shared". The cloning of derived messages is slightly changed as they previously relied on overriding the base-class through covariant return types.
2014-10-16base: Use shared_ptr for stat NodeAndreas Hansson
This patch transitions the stat Node and its derived classes from the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no changes in behaviour, and the code modifications are mainly replacing "new" with "make_shared".
2014-10-16base: Transition CP annotate to use shared_ptrAndreas Hansson
2014-10-16dev: Use shared_ptr for EthPacketDataAndreas Hansson
This patch transitions the EthPacketData from the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no changes in behaviour, and the code modifications are mainly replacing "new" with "make_shared". The bool casting operator for the shared_ptr is explicit, and we must therefore either cast it, compare it to NULL (p != nullptr), double negate it (!!p) or do a (p ? true : false).
2014-10-16dev: Use shared_ptr for Arguments::DataAndreas Hansson
This patch takes a first few steps in transitioning from the ad-hoc RefCountingPtr to the c++11 shared_ptr. There are no changes in behaviour, and the code modifications are mainly introducing the use of make_shared. Note that the class could use unique_ptr rather than shared_ptr, was it not for the postfix increment and decrement operators.
2014-10-16arch,x86,mem: Dynamically determine the ISA for Ruby store checkAndreas Hansson
This patch makes the memory system ISA-agnostic by enabling the Ruby Sequencer to dynamically determine if it has to do a store check. To enable this check, the ISA is encoded as an enum, and the system is able to provide the ISA to the Sequencer at run time. --HG-- rename : src/arch/x86/insts/microldstop.hh => src/arch/x86/ldstflags.hh
2014-10-16mem: Dynamically determine page bytes in memory componentsAndreas Hansson
This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA.
2014-10-16arm: Add helper methods to setup architected PMU eventsAndreas Sandberg
2014-10-16cpu: Probe points for basic PMU statsAndreas Sandberg
This changeset adds probe points that can be used to implement PMU counters for CPU stats. The following probes are supported: * BaseCPU::ppCycles / Cycles * BaseCPU::ppRetiredInsts / RetiredInsts * BaseCPU::ppRetiredLoads / RetiredLoads * BaseCPU::ppRetiredStores / RetiredStores * BaseCPU::ppRetiredBranches RetiredBranches
2014-10-16arm: Add TLB PMU probesAndreas Sandberg
This changeset adds probe points that can be used to implement PMU counters for TLB stats. The following probes are supported: * ArmISA::TLB::ppRefills / TLB Refills (TLB insertions)
2014-10-16cpu: Add branch predictor PMU probe pointsAndreas Sandberg
This changeset adds probe points that can be used to implement PMU counters for branch predictor stats. The following probes are supported: * BPRedUnit::ppBranches / Branches * BPRedUnit::ppMisses / Misses
2014-10-16arm: Add a model of an ARM PMUv3Andreas Sandberg
This class implements a subset of the ARM PMU v3 specification as described in the ARMv8 reference manual. It supports most of the features of the PMU, however the following features are known to be missing: * Event filtering (e.g., from different privilege levels). * Access controls (the PMU currently ignores the execution level). * The chain counter (event no. 0x1E) is unimplemented. The PMU itself does not implement any events, it merely provides an interface for the configuration scripts to hook up probes that drive events. Configuration scripts should call addEventProbe() to configure custom events or high-level methods to configure architected events. The Python implementation of addEventProbe() automatically delays event type registration until after instantiation. In order to support CPU switching and some combined counters (e.g., memory references synthesized from loads and stores), the PMU allows multiple probes per event type. When creating a system that switches between CPU models that share the same PMU, PMU events for all of the CPU models can be registered with the PMU. Kudos to Matt Horsnell for the initial gem5 implementation of the PMU.
2014-10-16sim: Add typedefs for PMU probe pointsAndreas Sandberg
In order to show make PMU probe points usable across different PMU implementations, we want a common probe interface. This patch the namespace ProbePoins that contains typedefs for probe points that are shared between multiple SimObjects. It also adds typedefs for the PMU probe interface.
2014-10-16sim: Add support for serializing BitUnionXXAndreas Sandberg
BitUnion instances can normally not be used with the SERIALIZE_SCALAR and UNSERIALIZE_SCALAR macros due to the way they are converted between their storage type and their actual type. This changeset adds a set of parm(In|Out) functions specifically for gem5 bit unions to work around the issue.
2014-10-16config: Add the ability to read a config file using C++ and PythonAndreas Hansson
This patch adds the ability to load in config.ini files generated from gem5 into another instance of gem5 built without Python configuration support. The intended use case is for configuring gem5 when it is a library embedded in another simulation system. A parallel config file reader is also provided purely in Python to demonstrate the approach taken and to provided similar functionality for as-yet-unknown use models. The Python configuration file reader can read both .ini and .json files. C++ configuration file reading: A command line option has been added for scons to enable C++ configuration file reading: --with-cxx-config There is an example in util/cxx_config that shows C++ configuration in action. util/cxx_config/README explains how to build the example. Configuration is achieved by the object CxxConfigManager. It handles reading object descriptions from a CxxConfigFileBase object which wraps a config file reader. The wrapper class CxxIniFile is provided which wraps an IniFile for reading .ini files. Reading .json files from C++ would be possible with a similar wrapper and a JSON parser. After reading object descriptions, CxxConfigManager creates SimObjectParam-derived objects from the classes in the (generated with this patch) directory build/ARCH/cxx_config CxxConfigManager can then build SimObjects from those SimObjectParams (in an order dictated by the SimObject-value parameters on other objects) and bind ports of the produced SimObjects. A minimal set of instantiate-replacing member functions are provided by CxxConfigManager and few of the member functions of SimObject (such as drain) are extended onto CxxConfigManager. Python configuration file reading (configs/example/read_config.py): A Python version of the reader is also supplied with a similar interface to CxxConfigFileBase (In Python: ConfigFile) to config file readers. The Python config file reading will handle both .ini and .json files. The object construction strategy is slightly different in Python from the C++ reader as you need to avoid objects prematurely becoming the children of other objects when setting parameters. Port binding also needs to be strictly in the same port-index order as the original instantiation.
2014-10-16scons: Add Undefined Behavior Sanitizer (UBSan) optionAndreas Hansson
This patch adds the Undefined Behavior Sanitizer (UBSan) for clang and gcc >= 4.9. Due to the performance impact, the usage is guarded by a command-line option.
2014-09-22scons: Add --without-tcmalloc build optionCurtis Dunham
Disabling tcmalloc is required for valgrind's memcheck to work properly; this option makes it easier to create such a build.
2014-08-12scons: Generate a single debug flag C++ fileCurtis Dunham
Reduces target count/compiler invocations by ~180.
2014-10-16scons: create dummy target to have SWIG generate C++ classesCurtis Dunham
scons build/<arch>/swig
2014-10-16config: Add a --without-python option to build processAndrew Bardsley
Add the ability to build libgem5 without embedded Python or the ability to configure with Python. This is a prelude to a patch to allow config.ini files to be loaded into libgem5 using only C++ which would make embedding gem5 within other simulation systems easier. This adds a few registration interfaces to things which cross between Python and C++. Namely: stats dumping and SimObject resolving
2014-10-16stats: Small bump of trailing statsAndreas Hansson
Somehow these seem to have been missed.
2014-10-11stats: updates due to changes to x86, stale configs.Nilay Vaish
2014-10-11cpu: Fix o3 SMT IQCount bugAndrew Lukefahr
Commmitted by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-11util: adds a script for using DSENTNilay Vaish
This patch adds a python script that processes the configuration and the statistics file from a simulation run. Configuration and activity of network routers and links obtained from this processing is fed to DSENT via its Python interface. DSENT then computes the area and the power consumption of these network components. The script outputs these quantities to the console.
2014-10-11ext: dsent: adds a Python interface, drops C++ oneNilay Vaish
This patch extensively modifies DSENT so that it can be accessed using Python. To access the Python interface, DSENT needs to compiled as a shared library. For this purpose a CMakeLists.txt file has been added. Some of the code that is not required is being removed.
2014-10-11ext: add the source code for DSENTNilay Vaish
This patch adds a tool called DSENT to the ext/ directory. DSENT is a tool that models power and area for on-chip networks. The next patch adds a script for using the tool.
2014-10-11ruby: network: garnet: add statistics for different activitiesNilay Vaish
This patch adds some statistics to garnet that record the activity of certain structures in the on-chip network. These statistics, in a later patch, will be used for computing the energy consumed by the on-chip network.
2014-10-11ruby: network: garnet: remove functions for computing powerNilay Vaish
2014-10-11ruby: drop Orion network power modelNilay Vaish
Orion is being dropped from ruby. It would be replaced with DSENT which has better models. Note that the power / energy numbers reported after this patch has been applied are not for use.
2014-10-11ruby: mesi: slight renamingNilay Vaish
2014-10-11config: separate function for instantiating a memory controllerNilay Vaish
This patch moves code for instantiating a single memory controller from the function config_mem() to a separate function. This is being done so that memory controllers can be instantiated without assuming that they will be attached to the system in a particular fashion.
2014-10-11ruby: structures: coorect #ifndef macros in header filesNilay Vaish
2014-10-11ruby: moesi hammer: correct typo in master-slave assignmentNilay Vaish
2014-06-13x86: add LongModeAddressSize function to cpuidJiuyue Ma
LongModeAddressSize was used by kernel 2.6.28.4 for physical address validation, if not properly implemented, PCI resource allocation may failed because of ioremap failed: - linux-2.6.28.4/arch/x86/mm/ioremap.c:27-30 27 static inline int phys_addr_valid(unsigned long addr) 28 { 29 return addr < (1UL << boot_cpu_data.x86_phys_bits); 30 } - linux-2.6.28.4/arch/x86/kernel/cpu/common.c:475-482 475 #ifdef CONFIG_X86_64 476 if (c->extended_cpuid_level >= 0x80000008) { 477 u32 eax = cpuid_eax(0x80000008); 478 479 c->x86_virt_bits = (eax >> 8) & 0xff; 480 c->x86_phys_bits = eax & 0xff; 481 } 482 #endif - linux-2.6.28.4/arch/x86/mm/ioremap.c:209-214 209 if (!phys_addr_valid(phys_addr)) { 210 printk(KERN_WARNING "ioremap: invalid physical address %llx\n", 211 (unsigned long long)phys_addr); 212 WARN_ON_ONCE(1); 213 return NULL; 214 } This patch return 0x0000ffff for LongModeAddressSize, which guarantee phys_addr_valid never failed. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-07-17config, x86: Ensure that PCI devs get bridged to the memory busJiuyue Ma
This patch force IO device to be mapped to 0xC0000000-0xFFFF0000 by reserve anything between the end of memory and 3GB if memory is less than 3GB. It also statically bridge these address range to the IO bus, which guaranty access to pci address space will pass though bridge to iobus. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-07-17config, x86: swap bus_id of ISA/PCI in X86 IntelMPTableJiuyue Ma
This patch assign bus_id=0 to PCI bus and bus_id=1 to ISA bus for X86 platform. Because PCI device get config space address using Pc::calcPciConfigAddr() which requires "assert(bus==0)". This fixes PCI interrupt routing and discovery on Linux. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-11sim: draining bug for fast-forwaring multiple coresAndrew Lukefahr
fix draining bug where multiple cores hit max_insts_any_thread simultaneously Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2014-10-11base: addr range: slight change to validity checkNilay Vaish
The validity check is being changed from < to <= since the end of the range is considered to be a part of it.
2014-10-11base: misc: Add missing header file.Nilay Vaish
2014-10-09stats: Add DRAM power statistics to reference outputAndreas Hansson
2014-07-29mem: DRAMPower integration for on-line DRAM power statsOmar Naji
This patch takes the final step in integrating DRAMPower and adds the appropriate calls in the DRAM controller to provide the command trace and extract the power and energy stats. The debug printouts are still left in place, but will eventually be removed. At the moment the DRAM power calculation is always on when using the DRAM controller model. The run-time impact of this addition is around 1.5% when looking at the total host seconds of the regressions. We deem this a sensible trade-off to avoid the complication of adding an enable/disable mechanism.