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AgeCommit message (Collapse)Author
2011-08-19O3: Update stats for LSQ changes.Ali Saidi
2011-08-19LSQ: Add some better dprintfs for storeset predictor.Mrinmoy Ghosh
2011-08-19LSQ: Fix a few issues with the storeset predictor.Mrinmoy Ghosh
Two issues are fixed in this patch: 1. The load and store pc passed to the predictor are passed in reverse order. 2. The flag indicating that a barrier is inflight was never cleared when the barrier was squashed instead of committed. This made all load insts dependent on a non-existent barrier in-flight.
2011-08-19Stats: Add a sparse histogram stat object.Thomas Grass
2011-08-19O3: Squash the violator and younger instructions instead not all insts.Giacomo Gabrielli
Change the way instructions are squashed on memory ordering violations to squash the violator and younger instructions, not all instructions that are younger than the instruction they violated (no reason to throw away valid work).
2011-08-19ARM: Add per-cpu local timers for ARM.Geoffrey Blake
Cortex-A9 processors can have a local timer and watchdog counter. It is enabled by default in Linux and up to this point we've had to disable them since a model wasn't available. This change allows a default MP ARM Linux configuration to boot.
2011-08-19ARM: Add per-processor interrupt support to GIC.Prakash Ramrakhani
2011-08-19ARM: Fix a memory leak with the table walker.Ali Saidi
2011-08-19Prefetcher: Fix some memory leaks with the prefetcher.Ali Saidi
2011-08-19ARM: quiet what can be a very noise CLCD controller.Ali Saidi
2011-08-16InOrder: Make cache_unit.hh include hashmap.hh explicitly, not transitively.Gabe Black
2011-08-16O3: Make lsq_unit.hh include arch/isa_traits.hh directly, not transitively.Gabe Black
2011-08-15Ruby: Initialize some variables.Nilay Vaish
2011-08-14X86: Add an X86_FS o3 regression.Gabe Black
2011-08-14O3: When squashing, restore the macroop that should be used for fetching.Gabe Black
2011-08-14O3: Add a pointer to the macroop for a microop in the dyninst.Gabe Black
2011-08-13Stats: Small update to stats for change to x86 inst flags.Gabe Black
2011-08-13X86: Use IsSquashAfter if an instruction could affect fetch translation.Gabe Black
Control register operands are set up so that writing to them is serialize after, serialize before, and non-speculative. These are probably overboard, but they should usually be safe. Unfortunately there are times when even these aren't enough. If an instruction modifies state that affects fetch, later serialized instructions which come after it might have already gone through fetch and decode by the time it commits. These instructions may have been translated incorrectly or interpretted incorrectly and need to be destroyed. This change modifies instructions which will or may have this behavior so that they use the IsSquashAfter flag when necessary.
2011-08-13O3: At the end of an instruction, force fetchAddr to something sensible.Gabe Black
It's possible (though until now very unlikely) for fetchAddr to get out of sync with the actual PC of the current instruction. This change forcefull resets fetchAddr at the end of every instruction.
2011-08-09SCons,tests: Tell scons about pc-o3-timing regressions.Gabe Black
2011-08-09X86: Build O3 by default in X86_FS.Gabe Black
2011-08-09Stats: Update stats for the end of macroop O3 fix.Gabe Black
2011-08-09O3: Stop using the current macroop no matter why you're leaving it.Gabe Black
Until now, the only reason a macroop would be left was because it ended at a microop marked as the last microop. In O3 with branch prediction, it's possible for the branch predictor to have entries which originally came from different instructions which happened to have the same RIP. This could theoretically happen in many ways, but it was encountered specifically when different programs in different address spaces ran one after the other in X86_FS. What would happen in that case was that the macroop would continue to be looped over and microops fetched from it until it reached the last microop even though the macropc had moved out from under it. If things lined up properly, this could mean that the end bytes of an instruction actually fell into the instruction sized block of memory after the one in the predecoder. The fetch loop implicitly assumes that the last instruction sized chunk of memory processed was the last one needed for the instruction it just finished executing. It would then tell the predecoder to move to an offset within the bytes it was given that is larger than those bytes, and that would trip an assert in the x86 predecoder. This change fixes this problem by making fetch stop processing the current macroop if the address it should be fetching from changed when the PC is updated. That happens when the last microop was reached because the instruction handled it properly, and it also catches the case where the branch predictor makes fetch do a macro level branch when it shouldn't. The check of isLastMicroop is retained because otherwise, a macroop that branches back to itself would act like a single, long macroop instead of multiple instances of the same microop. There may be situations (which may turn out to be purely hypothetical) where that matters. This also fixes a relatively minor issue where the curMacroop variable would be set to NULL immediately after seeing that a microop was the last one before curMacroop was used to build the dyninst. The traceData structure would have a NULL pointer to the macroop for that microop.
2011-08-09Stats: Update stats for the recent O3 interrupt change.Gabe Black
2011-08-09O3: When waiting to handle an interrupt, let everything drain out.Gabe Black
Before this change, the commit stage would wait until the ROB and store queue were empty before recognizing an interrupt. The fetch stage would stop generating instructions at an appropriate point, so commit would then wait until a valid time to interrupt the instruction stream. Instructions might be in flight after fetch but not the in the ROB or store queue (in rename, for instance), so this change makes commit wait until all in flight instructions are finished.
2011-08-08BuildEnv: Eliminate RUBY as build environment variableNilay Vaish
This patch replaces RUBY with PROTOCOL in all the SConscript files as the environment variable that decides whether or not certain components of the simulator are compiled.
2011-08-07O3: Get rid of the unused addToRemoveList function.Gabe Black
2011-08-07Stats: Update stats for the previous change.Gabe Black
2011-08-07O3: Let squashed and deferred instructions issue.Gabe Black
Let squahsed and deferred instructions issue so they don't accumulate and clog up the CPU.
2011-08-07Stats: Update the stats after the uninitialized branch predictor variable fix.Gabe Black
2011-08-07O3: Fix uninitialized variable in the tournament branch predictor.Ali Saidi
2011-08-07Translation: Use a pointer type as the template argument.Gabe Black
This allows regular pointers and reference counted pointers without having to use any shim structures or other tricks.
2011-08-03Ruby: Remove files and includes not in useNilay Vaish
2011-08-02O3: Get rid of the raw ExtMachInst constructor on DynInsts.Gabe Black
This constructor assumes that the ExtMachInst can be decoded directly into a StaticInst that's useful to execute. With the advent of microcoded instructions that's no longer true.
2011-08-02Scons: Make some Action objects fit the abreviated output format.Gabe Black
2011-08-02Scons: Drop RUBY as compile time option.Nilay Vaish
This patch drops RUBY as a compile time option. Instead the PROTOCOL option is used to figure out whether or not to build Ruby. If the specified protocol is 'None', then Ruby is not compiled.
2011-07-31O3: Implement memory mapped IPRs for O3.Gabe Black
2011-07-30Stats: Update stats for the recent fix to fetch.Gabe Black
2011-07-30O3: Fix corner case squashing into the microcode ROM.Gabe Black
When fetching from the microcode ROM, if the PC is set so that it isn't in the cache block that's been fetched the CPU will get stuck. The fetch stage notices that it's in the ROM so it doesn't try to fetch from the current PC. It then later notices that it's outside of the current cache block so it skips generating instructions expecting to continue once the right bytes have been fetched. This change lets the fetch stage attempt to generate instructions, and only checks if the bytes it's going to use are valid if it's really going to use them.
2011-07-27SLICC: Put functions of a controller in its .cc fileNilay Vaish
Currently, functions associated with a controller go into separate files. This patch puts all the functions in the controller's .cc file. This should hopefully take away some time from compilation.
2011-07-26Ruby: Fix instantiations of DMA controller and sequencerNilay Vaish
The patch on Ruby functional accesses made changes to the process of instantiating controllers and sequencers. The DMA controller and sequencer was not updated, hence this patch.
2011-07-25Merged with Gabe's changeset.Nilay Vaish
2011-07-25Ruby: Fix dma controller configs/ruby/MI_example.pyNilay Vaish
The dma controller in configs/ruby/MI_example.py was not being set correctly. This patch fixes it.
2011-07-19SCons: Only print all the SConsopts being read if verbose is turned on.Gabe Black
2011-07-15inorder-fs: temp. regression removalKorey Sewell
remove this regression till the fix for the hwrei instruction is put in
2011-07-15Mem: Fix issue with prefetches originating at non-L1 caches getting stale dataAli Saidi
Prefetch requests issued from the L2 or below wouldn't check if valid data is present higher in the system. If a prefetch into the L2 occured at the same time as writeback from a higher-level cache the dirty data could be replaced in by unmodified data in memory.
2011-07-15O3: Create a pipeline activity viewer for the O3 CPU model.Giacomo Gabrielli
Implemented a pipeline activity viewer as a python script (util/o3-pipeview.py) and modified O3 code base to support an extra trace flag (O3PipeView) for generating traces to be used as inputs by the tool.
2011-07-15ARM: Update stats for better miscreg support for MP configurations.Ali Saidi
2011-07-15ARM: Fix SWP/SWPB undefined instruction behaviorWade Walker
SWP and SWPB now throw an undefined instruction exception if SCTLR.SW == 0. This also required the MIDR to be changed slightly so programs can correctly determine that gem5 supports the ARM v7 behavior of SWP/SWPB (in ARM v6, SWP/SWPB were deprecated, but not disabled at CPU startup).
2011-07-15ARM: Add two unimplemented miscellaneous registers.Wade Walker
Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both registers now return values that are consistent with current ARM implementations.