Age | Commit message (Collapse) | Author |
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we can make our own hypervisor binary, we probably won't need it.
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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formatting functions.
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manual of what happens during a trap says it should be 0, and other places say it doesn't matter.
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description.
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src/cpu/o3/alpha/cpu_impl.hh:
Handle the PhysicalPort and VirtualPort in the ThreadState.
src/cpu/o3/cpu.cc:
Initialize the thread context.
src/cpu/o3/thread_context.hh:
Add new function to initialize thread context.
src/cpu/o3/thread_context_impl.hh:
Use code now put into function.
src/cpu/simple_thread.cc:
Move code to ThreadState and use the new helper function.
src/cpu/simple_thread.hh:
Remove init() in this derived class; use init() from ThreadState base class.
src/cpu/thread_state.cc:
Move setting up of Physical and Virtual ports here. Change getMemFuncPort() to connectToMemFunc(), which connects a port to a functional port of the memory object below the CPU.
src/cpu/thread_state.hh:
Update functions.
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extra : convert_revision : ff254715ef0b259dc80d08f13543b63e4024ca8d
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 1fc55d7d5707bb7c63790aab306ca5ea8ade5fab
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[phys,virt]Port correctly
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Call the thread context initialization
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only once.
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CPU2000 stuff, and use it in all of the tests that currently
use SPEC
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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into zower.eecs.umich.edu:/home/gblack/m5/newmemmemops
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configs/common/FSConfig.py:
Make a SPARC system create an IO bus.
src/python/m5/objects/T1000.py:
Create a T1000 platform
src/arch/sparc/miscregfile.cc:
Initialize the strand status register to the value legion provides.
src/cpu/exetrace.cc:
Truncate an ExtMachInst to a MachInst before comparing with Legion.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 8d61b474428d494b1a5382e4cf95934ad54e35dd
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src/cpu/simple/timing.cc:
Various updates for deleting requests more properly.
The major change is moving the deletion of the fetch request/packet to after the instruction has executed and completed. This should fix a few bugs because Ron's memory system didn't expect a call for a functional access while a timing access was being processed.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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src/mem/bus.cc:
Make it so that invalidates being sent from the responder up don't call the responder
but they should also not Panic.
src/mem/packet.hh:
If we don't have data in the packet, don't call deleteData:
Example: InvalidateRequests never have data.
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extra : convert_revision : 18766bc9f3bb4d852ac651d094254d347abd1634
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
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into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
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make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build
src/arch/sparc/interrupts.hh:
make a likewise updateIntrInfo for Sparc that's blank so it doesn't fart on build
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
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src/mem/bridge.cc:
Update brdiges, now that snoop addresses are properly forwarded.
Bus bridge should only handle snoops on the second phase (SNOOP_COMMIT)
src/mem/bus.cc:
src/mem/bus.hh:
Make sure if a busBridge has access to both things that snoop and things that respond it only takes the request once
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sendTiming has not returned in the call stack.
src/mem/cache/base_cache.cc:
Sometimes a functional access comes while waiting on a outstanding packet being sent.
This could be because Timing CPU does some post processing on the recvTiming which send functional access.
Either the CPU should leave the pkt/req around (so They can be referenced in the mem system). Or the mem
system should remove them from outstanding lists and reinsert them if they fail in the sendTiming.
I did the later, eventually we should consider doing the former if that is the correct behavior.
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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src/mem/bus.cc:
Only call snoop once per port, need to fix it so snoop ranges that overlap aren't added to list
Functional accesses that call snoop and it goes to a higher bus may change the src, reset it after each snoop.
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src/mem/bus.cc:
Actually return the snoop list when asked for it.
Don't get stuck in infinite functional loops
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extra : convert_revision : 8e6dafbd10b30d48d28b6b5d4b464e8e8f6a3ddc
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src/cpu/simple/atomic.cc:
Make the atomic cpu return 0 on snoops.
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swig still thought the default arg for simulate() was -1, make it MaxTick
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configs/splash2/run.py:
Fix MaxTick for splash configs
configs/splash2/cluster.py:
Add a config that allows clusters of CPU's to be attached to a single L1
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the Debug param context
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