Age | Commit message (Collapse) | Author |
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into zeep.pool:/z/saidi/work/m5.newmem.head
src/mem/packet.hh:
hand merge
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extra : convert_revision : 3f77707360235dc98c6b12a0367ca64a401313df
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implement fix packet and add the ability to print a packet to a ostream
remove tabs in packet.hh (Could people stop inserting them??!?!?!)
mark const functions in packet.hh as such
src/base/traceflags.py:
add a traceflag for functional accesses
src/mem/packet.cc:
implement fix packet and add the ability to print a packet to a ostream
src/mem/packet.hh:
add the ability to print a packet to an ostream
remove tabs in file
mark const functions as such
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extra : convert_revision : 4297bce5e1d3abbab48be5bd9eb9e982b751fc7c
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The response queue is not tying up an MSHR, should we change that or assume infinite storage for responses?
src/mem/cache/base_cache.cc:
src/mem/tport.cc:
Add in functional check of retry queued packets.
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extra : convert_revision : 0cb40b3a96d37a5e9eec95312d660ec6a9ce526a
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src/cpu/memtest/memtest.cc:
Another memleak in the memtester
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extra : convert_revision : f7ab079e90d578fb6b9d1ff238d049fcce55b01b
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extra : convert_revision : 93062b0f1a3ba7a5210e2f27099f20ae8f66522b
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src/base/traceflags.py:
src/mem/physical.cc:
Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
Set the size properly on unCacheable accesses
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extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : b6224624ea493531e5ecc161bede7433f96d8a0f
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Fix a segfault associated with DefaultId
src/mem/bus.cc:
Handle a segfault in the bus when DefaultPort was being used
src/mem/bus.hh:
Make the Default ID more unique (it overlapped with Broadcast ID)
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extra : convert_revision : 9182805c5cf4d9fe004e6c5be8547a8f41ed7bfe
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extra : convert_revision : 619d6af7013b597ade6440f8cf84d6d099e31763
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src/mem/bus.cc:
Add debugging statement
src/mem/bus.hh:
Fix implementation of bus for subsequent recvTimings while handling a retry request.
src/mem/tport.cc:
Rework timing port to retry properly
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extra : convert_revision : f5197172b094d59ced84423eb34c31ddf23689ee
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extra : convert_revision : 5e105d7082a8c103fb5d5383c3093734bfd590f5
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- this fixes it so that changeToTiming/changeToAtomic works.
src/python/m5/SimObject.py:
now that setMemoryMode is a method in System, need to convert the SimObject * _ccObject into a system ptr to call setMemoryMode.
src/sim/main.cc:
need this conversion now.
src/sim/sim_object.hh:
put the enum back into SimObject.
src/sim/system.hh:
memoryMode is now a part of SimObject, need the ::'s
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extra : convert_revision : 0ade06957fa57b497798e1f50c237ca1badc821d
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changes so that when you come out of resume, you only assert if you're really wrong.
src/cpu/simple/atomic.cc:
memory mode assertion change so that it only goes off if it's supposed to.
src/cpu/simple/timing.cc:
some drain changes (kevin's) and some changes to memoryMode assertions so that they don't go off when they're not supposed to.
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extra : convert_revision : 007d8610f097e08f01367b905ada49f93cf37ca3
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src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
Debug output.
Clean up memleak in atomic mode.
Set hitLatency.
Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
Add command strings for new commands
src/python/m5/objects/MemTest.py:
Add param to test atomic memory.
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extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b
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extra : convert_revision : 6a23052056d1c61cba0a4c77f1030cee419c6fa3
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Get over 500,000 reads on each of 8 testers before memory leak becomes large.
tests/configs/memtest.py:
Update test to be more interesting
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extra : convert_revision : 4258b798fbeeed2a376f1bfac100a109eb05620e
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 70187b8f04d0f8424512f64bdade05bf1aca85a3
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Fix bug with deadlocking
src/mem/cache/base_cache.cc:
Make sure to not wait anymore
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extra : convert_revision : 5f7b44a1c475820b9862275a0d6113ec2991735d
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case as well when dealing with grants that aren't used.
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extra : convert_revision : 38f7ef1b41477fb2a2438387ef3a81cccd3e7a8a
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : d2d19b27533f35c6570ee84c6c83b2919f27b97f
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some reason.
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extra : convert_revision : e722ddb0354a5c021dc7c44a3e2f0a64e962442b
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src/mem/cache/base_cache.cc:
When turning asserts into if's don't forget to invert.
Must be too sleepy.
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extra : convert_revision : ea38d5a4b4ddde7b5266b3b2c83bbc256218af9a
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uprgades to owned blocks hit in the WB buffer
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extra : convert_revision : f0502836a79ce303150daa7e571badb0bce3a97a
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--HG--
extra : convert_revision : 511c0bcd44b93d5499eefa8399f36ef8b6607311
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/bus.cc:
SCCS merged
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extra : convert_revision : 18608114350c466a56ab499ae523b01fcb2f6ef2
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--HG--
extra : convert_revision : aef3c625172e92be8f29c4c57077fefee43046bb
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/bus.cc:
SCCS merged
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extra : convert_revision : eaae105025635c37af06cf72bb061ce82def9dc9
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src/base/traceflags.py:
Add new flags for cacheport
src/mem/bus.cc:
Add debugging info
src/mem/cache/base_cache.cc:
Add debuggin info
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extra : convert_revision : a6c4b452466a8e0b50a86e886833cb6e29edc748
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try to send another packet while it's still waiting for the bus.
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extra : convert_revision : 4a2b83111e49f71ca27e05c98b55bc3bac8d9f53
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--HG--
extra : convert_revision : b57c31ca7c220e701d34e02bb07ce392370e4428
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 7b7a1b03ffed36bce49595962ea57c08d1d1a4ad
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src/mem/cache/base_cache.cc:
Add sanity checks
src/mem/cache/base_cache.hh:
Fix for retry mechanism
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extra : convert_revision : 9298e32e64194b1ef3fe51242595eaa56dcbbcfd
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src/mem/tport.cc:
minor formatting tweak
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extra : convert_revision : 7391d142815c5876fcc0f991bd053e6a1781c101
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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extra : convert_revision : aa59d3169d84bcd13b8c97f22b52aeef43dc33c3
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Update retry mechanism
src/mem/cache/base_cache.cc:
Rework the retry mechanism
src/mem/cache/base_cache.hh:
Rework the retry mechanism
Try to fix memory bug
src/mem/cache/cache_impl.hh:
Rework upgrades to not be blocked by slave
src/mem/cache/miss/mshr_queue.cc:
Fix mem leak on writebacks
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extra : convert_revision : 3cec234ee441edf398ec8d0f51a0c5d7ada1e2be
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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extra : convert_revision : 4036e8447fb3038d93285c6582900210d7d88d67
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Fix Upgrades being blocked by slave
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extra : convert_revision : cca98a38e32233145163577500f1362cd807ab15
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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extra : convert_revision : 6027c395af044858465eafd3ea78bcfe4c923bcc
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
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extra : convert_revision : 8b27fc92f8aafe691d70dc654bff3798abf8e755
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tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout:
Update refs.
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extra : convert_revision : 5341341507ddbe1211992e5f72013d7be0000bae
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 87f83c4edf6ea51adc767d98265d1e74c0fbb46f
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--HG--
extra : convert_revision : dcf0d7eafa5168591c2b374b452821ca34dde7f9
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extra : convert_revision : 129dadbf8091ab00fb7f16eace59df265fc3718c
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--HG--
extra : convert_revision : 2b33da5e8578ea6a8bdd2d89f183c2e6b942b0fc
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/packet.hh:
Hand merge code
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extra : convert_revision : d659418f24f4f4bf9867fec8573a5d227c0dfcea
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configs/common/SysPaths.py:
Undo accidental change.
src/SConscript:
Fix.
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extra : convert_revision : 665b186cff7d8ae560601ced7ae407a41a16cfea
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src/mem/cache/base_cache.cc:
Fix a bug about not having a request to send
src/mem/cache/base_cache.hh:
Fix a bug with the blocking code
src/mem/cache/cache.hh:
AFix a bug with snoop hits in WB buffer
src/mem/cache/cache_impl.hh:
Fix a bug with snoop hits in WB buffer
Also, add better DPRINTF's
src/mem/cache/miss/miss_queue.cc:
Fix a bug with upgrades (Need to clean it up later)
src/mem/cache/miss/mshr.cc:
Fix a memory leak bug, still some outstanding with writebacks not being deleted
src/mem/cache/miss/mshr_queue.cc:
Fix a bug about upgrades (need to clean up later)
src/mem/packet.hh:
Fix for newly added cmd attribute for upgrades
tests/configs/memtest.py:
More interesting testcase
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extra : convert_revision : fcb4f17dd58b537bb4f67a8c835f50e455e8c688
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packet was waiting for the bus.
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extra : convert_revision : 29f7a4f676884330d7b7e93517dea85fc7bbf678
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