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AgeCommit message (Expand)Author
2018-06-07dev-arm: Add a GIC interrupt adaptorAndreas Sandberg
2018-06-06arch-arm: Remove dead doingStage2 variable in PT walkerAndreas Sandberg
2018-06-06system-arm: Update gem5 timer interrupt specificationAndreas Sandberg
2018-06-06arch-arm: Perform stage 2 lookups using the EL2 stateAndreas Sandberg
2018-06-06arch-arm: Respect EL from translation typeAndreas Sandberg
2018-06-06arch-arm: Fix page size handling when merging stage 1 and 2Andreas Sandberg
2018-06-06dev, arm: Add support for HYP & secure timersAndreas Sandberg
2018-06-06arch-arm: Adjust breakpoint EC depending on source stateAndreas Sandberg
2018-06-01mem-cache: Privatize extractSetDaniel R. Carvalho
2018-06-01mem-cache: Create an address aware TempCacheBlkDaniel R. Carvalho
2018-06-01mem-cache: Fix secure bit modificationDaniel R. Carvalho
2018-05-31mem-cache: Replace block visitor with std::functionNikos Nikoleris
2018-05-31mem-cache: Fix include directives in the cache related classesNikos Nikoleris
2018-05-31mem-cache: Add a non-coherent cacheNikos Nikoleris
2018-05-31mem-cache: Move cache bypass mechanism to the portsNikos Nikoleris
2018-05-31mem-cache: Adopt a more sensible cache class hierarchyNikos Nikoleris
2018-05-31mem-cache: Add helper function to perform evictionsNikos Nikoleris
2018-05-31mem-cache: Delegate block invalidation to block allocationNikos Nikoleris
2018-05-31mem-cache: Refactor the recvAtomic functionNikos Nikoleris
2018-05-31mem-cache: Refactor the cache recvTimingReq functionNikos Nikoleris
2018-05-31mem-cache: Refactor the cache recvTimingResp functionNikos Nikoleris
2018-05-31mem-cache: Fix RandomReplDataDaniel R. Carvalho
2018-05-30gpu-compute: use X86ISA::TlbEntry over GpuTlbEntryBrandon Potter
2018-05-30dev: Exit correctly in dist-gem5 for SE modeMichael LeBeane
2018-05-30mem-cache: Determine if an MSHR has requests from another cacheNikos Nikoleris
2018-05-29arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOPGiacomo Travaglini
2018-05-29arch-arm: Remove unusued MISCREG_A64_UNIMPLGiacomo Travaglini
2018-05-29arch-arm: MPIDR.MT = 1 in a multithreaded systemGiacomo Travaglini
2018-05-29arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation definedGiacomo Travaglini
2018-05-29cpu: Avoid unnecessary dynamic_pointer_cast in atomic modelGiacomo Travaglini
2018-05-29arch-arm: Implement ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
2018-05-29arch-arm: Add E2H bit to HCR_EL2 System registerGiacomo Travaglini
2018-05-24x86: Add op classes to the MediaOps.Gabe Black
2018-05-18mem: Add support for more flexible DRAM timing and topologiesWendy Elsasser
2018-05-18mem: Optimize self-refresh entryWendy Elsasser
2018-05-17mem-cache: Move reference count stats update to blk invalidationNikos Nikoleris
2018-05-17mem-cache: Remove isTouched field from the CacheBlkNikos Nikoleris
2018-05-17mem-cache: Move replacements stat to the base cache classNikos Nikoleris
2018-05-17base: Add M5 flag for [[nodiscard]] attributeNikos Nikoleris
2018-05-17mem-cache: Simplify writeback for the tempBlock in recvTimingRespNikos Nikoleris
2018-05-16arch-arm: Fix semihosting arg count for SYS_GET_CMDLINEAndreas Sandberg
2018-05-16arch-arm: Add support for semihosting STDIO redirectionAndreas Sandberg
2018-05-16style: fix amd license and style issuesTony Gutierrez
2018-05-15gpu-compute: Cleanup the scheduler a bitTony Gutierrez
2018-05-12arch-riscv: Update CSR implementationsAlec Roelke
2018-05-09sim: Remove trailing dot when assigning a master's nameGiacomo Travaglini
2018-05-09base, dev: Fix port message for vnc and terminalAndreas Sandberg
2018-05-08arch-x86, arch-power: fix calls to bits and insertBitsMatt Sinclair
2018-05-08mem-cache: Create block insertion functionDaniel R. Carvalho
2018-05-08arch-arm: Map ID_x_EL1 registers to AArch32 versionGiacomo Travaglini
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