gem5 - gem5

Age	Commit message (Expand)	Author
2013-03-01	mem: Add check if SimpleDRAM nextReqEvent is scheduled	Andreas Hansson
2013-03-01	mem: Add a method to build multi-channel DRAM configurations	Andreas Hansson
2013-03-01	stats: Update stats to reflect SimpleDRAM changes	Andreas Hansson
2013-03-01	mem: SimpleDRAM variable naming and whitespace fixes	Andreas Hansson
2013-03-01	mem: Add support for multi-channel DRAM configurations	Andreas Hansson
2013-03-01	mem: Merge interleaved ranges when creating backing store	Andreas Hansson
2013-03-01	mem: Merge ranges in bus before passing them on	Andreas Hansson
2013-02-28	ruby: mesi coherence protocol: invalidate lock	Dibakar Gope ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E)
2013-02-20	config: Fix --prog-interval command line option	Ali Saidi
2013-02-19	slicc: remove unused variable message_buffer_names	Nilay Vaish
2013-02-19	ruby: remove unused variable m_print_config in class Topology	Nilay Vaish
2013-02-19	mem: Fix sender state bug and delay popping	Andreas Hansson
2013-02-19	stats: more zizzer stats fun	Ali Saidi
2013-02-19	scons: Fix warnings issued by clang 3.2svn (XCode 4.6)	Andreas Hansson
2013-02-19	scons: Unify the flags shared by gcc and clang	Andreas Hansson
2013-02-19	scons: Add warning delete with non-virtual destructor	Andreas Hansson
2013-02-19	scons: Add warning for missing declarations	Andreas Hansson
2013-02-19	scons: Add warning for overloaded virtual functions	Andreas Hansson
2013-02-19	scons: Add warning for overloaded virtual functions	Andreas Hansson
2013-02-19	scons: Add warning for missing field initializers	Andreas Hansson
2013-02-19	scons: Fix up numerous warnings about name shadowing	Andreas Hansson
2013-02-19	mem: Enforce strict use of busFirst- and busLastWordTime	Andreas Hansson
2013-02-19	mem: Change accessor function names to match the port interface	Andreas Hansson
2013-02-19	mem: Make packet bus-related time accounting relative	Andreas Hansson
2013-02-19	mem: Add deferred packet class to prefetcher	Andreas Hansson
2013-02-19	sim: Make clock private and access using clockPeriod()	Andreas Hansson
2013-02-19	x86: Move APIC clock divider to Python	Andreas Hansson
2013-02-19	mem: Fix SenderState related cache deadlock	Sascha Bischoff
2013-02-19	mem: Add predecessor to SenderState base class	Andreas Hansson
2013-02-19	base: Fix a bug in the address interleaving	Andreas Hansson
2013-02-19	mem: Ensure trace captures packet fields before forwarding	Andreas Hansson
2013-02-15	options: add command line option for dtb file	Anthony Gutierrez
2013-02-15	loader: add a flattened device tree blob (dtb) object	Anthony Gutierrez
2013-02-15	ext lib: add libfdt to enable flattened device tree support	Anthony Gutierrez
2013-02-15	stats: update regressions for o3 changes in renaming and translation.	Ali Saidi
2013-02-15	arm: fix a page table walker issue where a page could be translated multiple ...	Mrinmoy Ghosh
2013-02-15	cpu: Document exec trace flags	Andreas Sandberg
2013-02-15	dev: Use the correct return type for disk offsets	Andreas Sandberg
2013-02-15	cpu: Avoid duplicate entries in tracking structures for writes to misc regs	Geoffrey Blake
2013-02-15	cpu: Fix rename mis-handling serializing instructions when resource constrained	Geoffrey Blake
2013-02-15	ARM: Postpones creation of framebuffer output file until it is actually used.	Chris Emmons
2013-02-15	mem: Tighten up cache constness and scoping	Andreas Hansson
2013-02-15	base: Add warn() and inform() to m5.utils for use from python	Sascha Bischoff
2013-02-15	o3: fix tick used for renaming and issue with range selection	Matt Horsnell
2012-10-25	arm: Don't export private GIC methods	Andreas Sandberg
2012-10-25	arm: Create a GIC base class and make the PL390 derive from it	Andreas Sandberg
2013-02-15	sim: Add a system-global option to bypass caches	Andreas Sandberg
2013-02-15	cpu: Refactor memory system checks	Andreas Sandberg
2013-02-15	config: Remove O3 dependencies	Andreas Sandberg
2013-02-15	config: Move CPU handover logic to m5.switchCpus()	Andreas Sandberg