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2016-08-24commit 15c633eea52f21dae8cb3a195823b3cdec7be491Curtis Dunham
Author: Curtis Dunham <Curtis.Dunham@arm.com> ext: update SST connector for SST 6.0
2016-08-22config: KVM acceleration for apu_se.pyDavid Hashe
Add support for using KVM to accelerate APU simulations. The intended use case is to fast-forward through runtime initialization until the first kernel launch.
2016-08-22tests: Add example of using KVM acceleration with an appDavid Hashe
Add #ifdef's to gpu-hello.cpp demonstrating how to annotate an application for KVM acceleration.
2016-08-22cpu, mem, sim: Change how KVM maps memoryDavid Hashe
Only map memories into the KVM guest address space that are marked as usable by KVM. Create BackingStoreEntry class containing flags for is_conf_reported, in_addr_map, and kvm_map.
2016-08-16dev: Revert 0a316996de76 [dev, sim: Added missing override...]Andreas Sandberg
This changeset reverts the changset "dev, sim: Added missing override keywords to fix CLANG compilation (OSX)" which was incorrectly rebased. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-15cpu: Add missing override in Minor's exec contextAndreas Sandberg
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-15cpu: Fixed clang errors. Added 'override' keyword for virtual functions.Reiley Jeapaul
Change-Id: Ic37311443ca11ee6d95bceffea599e054e7aa110 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-15mem: Print an MSHR without triggering any assertionsNikos Nikoleris
Previously printing an mshr would trigger an assertion if the MSHR was not in service or if the targets list was empty. This patch changes the print function to bypasses the accessor functions for postInvalidate and postDowngrade and avoid the relevant assertions. It also checks if the targets list is empty before calling print on it. Change-Id: Ic18bee6cb088f63976112eba40e89501237cfe62 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-15dev, sim: Added missing override keywords to fix CLANG compilation (OSX)Matteo Andreozzi
Change-Id: Ice5fa11e77d06576eaa42149f5fa340a769d8b01 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
Change-Id: I183b9942929c873c3272ce6d1abd4ebc472c7132 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-13tests: remove EIO testsSteve Reinhardt
An email sent to gem5-users and gem5-dev asking if anyone was still using EIO traces got no responses, so it seems like it's not worth maintaining this any longer.
2016-08-12stats: Update to match classic memory changesAndreas Sandberg
2016-08-12mem: Add support for secure packets in the snoop filterNikos Nikoleris
Secure and non-secure data can coexist in the cache and therefore the snoop filter should treat differently packets with secure and non secure accesses. This patch uses the lower bits of the line address to keep track of whether the packet is addressing secure memory or not. Change-Id: I54a5e614dad566a5083582bede86c86896f2c2c1 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
2016-08-12mem: Add snoop filter to SystemXBar by defaultAndreas Hansson
This patch changes the default behaviour of the SystemXBar, adding a snoop filter. With the recent updates to the snoop filter allocation behaviour this change no longer causes problems for the regressions without caches. Change-Id: Ibe0cd437b71b2ede9002384126553679acc69cc1 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
2016-08-12mem: Use FromCache attribute in snoop filter allocationAndreas Hansson
This patch improves the snoop filter allocation decisions by not only looking at whether a port is snooping or not, but also if the packet actually came from a cache. The issue with only looking at isSnooping is that the CPU ports, for example, are snooping, but not actually caching. Previously we ended up incorrectly allocating entries in systems without caches (such as the atomic and timing quick regressions). Eventually these misguided allocations caused the snoop filter to panic due to an excessive size. On the request path we now include the fromCache check on the packet itself, and for responses we check if we actually have a snoop-filter entry. Change-Id: Idd2dbc4f00c7e07d331e9a02658aee30d0350d7e Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
2016-08-12mem: Update mostly exclusive policy even furtherAndreas Hansson
This patch takes yet another step in maintaining the clusivity, in that it allows a mostly-inclusive cache to hold on to blocks even when responding to a ReadExReq or UpgradeReq. Previously the cache simply invalidated these blocks, but there is no strict need to do so. The most important part of this patch is that we simply mark the block clean when satisfying the upstream request where the cache is allowed to keep the block. The only tricky part of the patch is in the memory management of deferred snoops, where we need to distinguish the cases where only the packet was copied (we expected to respond), and the cases where we created an entirely new packet and request (we kept it only to replay later). The code in satisfyRequest is definitely ready for some refactoring after this. Change-Id: I201ddc7b2582eaa46fb8cff0c7ad09e02d64b0fc Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
2016-08-12mem: Update mostly exclusive cache policy to cover more casesAndreas Hansson
This patch changes how the mostly exclusive policy is enforced to ensure that we drop blocks when we should. As part of this change, the actual invalidation due to the clusivity enforcement is moved outside the hit handling, to a separate method maintainClusivity. For the timing mode that means we can deal with all MSHR targets before taking any action and possibly dropping the block. The method satisfyCpuSideRequest is also renamed satisfyRequest as part of this change (since we only ever see requests from the cpu-side port). Change-Id: If6f3d1e0c3e7be9a67b72a55e4fc2ec4a90fd3d2 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
2016-08-12mem: Add a FromCache packet attributeAndreas Hansson
This patch adds a FromCache attribute to the packet, and updates a number of the existing request commands to reflect that the request originates from a cache. The attribute simplifies checking if a requests came from a cache or not, and this is used by both the cache and snoop filter in follow-on patches. Change-Id: Ib0a7a080bbe4d6036ddd84b46fd45bc7eb41cd8f Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Steve Reinhardt <stever@gmail.com>
2016-08-10arm, config: Exit with fatal error if using RubyAndreas Sandberg
Ruby on ARM is currently very experimental. Fail with a fatal error that explains this to make sure users are aware of the limitations (it doesn't actually work yet!). Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-10arm, config: Add initial support for RubyAndreas Sandberg
Add initial support for creating an ARM system with a Ruby-based memory system. This support is currently experimental and limited to the new VExpress_GEM5_V1 platform. Change-Id: I36baeb68b0d891e34ea46aafe17b5e55217b4bfa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
2016-08-10arm, dev: Add support for listing DMA ports in new platformsAndreas Sandberg
When using a Ruby memory system, the Ruby configuration scripts expect to get a list of DMA ports to create the necessary DMA sequencers. Add support in the utility functions that wire up devices to append DMA ports to a list instead of connecting them to the IO bus. These functions are currently only used by the VExpress_GEM5_V1 platform. Change-Id: I46059e46b0f69e7be5f267e396811bd3caa3ed63 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
2016-08-10ruby: Implement support for functional accesses to PIO rangesAndreas Sandberg
There are cases where we want to put boot ROMs on the PIO bus. Ruby currently doesn't support functional accesses to such memories since functional accesses are always assumed to go to physical memory. Add the required support for routing functional accesses to the PIO bus. Change-Id: Ia5b0fcbe87b9642bfd6ff98a55f71909d1a804e3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brad Beckmann <brad.beckmann@amd.com> Reviewed-by: Michael LeBeane <michael.lebeane@amd.com>
2016-08-10arm: Don't report the boot ROM as a memory in config tablesAndreas Sandberg
The boot ROM shouldn't be used as a memory by the kernel. Memories have a flag to indicate this which is set for some platforms. Update all platforms to consistently set this flag to indicate that the boot ROM shouldn't be reported as normal memory. Change-Id: I2bf0273e99d2a668e4e8d59f535c1910c745aa7b Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Brad Beckmann <brad.beckmann@amd.com> --HG-- extra : amend_source : c2cbda38636ea37cbe9ae6977a06b923eab5ba56
2016-08-05sim: fix issues with pwrite(); don't enable fstatfsTony Gutierrez
this patch fixes issues with changeset 11593 use the host's pwrite() syscall for pwrite64Func(), as opposed to pwrite64(), because pwrite64() does not work well on all distros. undo the enabling of fstatfs, as we will add this in a separate pate.
2016-08-04x86, sim: add some syscalls to X86Tony Gutierrez
this patch adds an implementation for the pwrite64 syscall and enables it for x86_64, and enables fstatfs for x86_64.
2016-08-03style: Make the style fixers safeJason Lowe-Power
Adds a wrapper to the fix functions of the verifiers. This wrapper first copies the original file to a backup file, then performs the fix. If an error occurs, the backup file is used to restore the original file. Also fixed a line-length error in verifiers.py
2016-08-02arm: s/ctx_id/ctx/ the GICCurtis Dunham
Factored out of the larger banked register change. Change-Id: I947dbdb9c00b4678bea9d4f77b913b7014208690 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-02arm: bank GIC registers per CPUCurtis Dunham
Updated according to GICv2 documentation. Change-Id: I5d926d1abf665eecc43ff0f7d6e561e1ee1c390a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-08-02stats: update referencesCurtis Dunham
2016-08-02arm: refactor page table walkingCurtis Dunham
Introduce and use a lookup table. Using fetchDescriptor() rather than DMA cleanly handles nested paging. Change-Id: I69ec762f176bd752ba1040890e731826b58d15a6
2016-08-02arm: warn not fail on use of missing miscreg CNTHCTL_EL2Dylan Johnson
During host bootup, KVM reads/writes to CNTHCTL_EL2. Because this miscreg has not been implemented, the simulation would end there. This patch causes the simulation to warn about the read/write instead of fail. Change-Id: If034bfd0818a9a5e50c5fe86609e945258c96fa3
2016-08-02arm: Check TLB stage 2 permissions in AArch64Dylan Johnson
This fixes a bug where stage 2 lookups used the AArch32 permissions rules even if we were executing in AArch64 mode. Change-Id: Ia40758f0599667ca7ca15268bd3bf051342c24c1
2016-08-02arm: correctly assign faulting IPA's to HPFAR_EL2Dylan Johnson
This patch corrects IPA reporting if the translation faults in a stage 2 lookup. Change-Id: I0b914527f8a9f98a5e980a131cf9d03e5584b4e9
2016-08-02arm: Add TLBI instruction for stage 2 IPA'sDylan Johnson
This patch adds support for stage 2 TLBI instructions such as TLBI IPAS2E1_Xt. Change-Id: I0cd5e8055b0c1003e03439aa5183252f50ea0a88
2016-08-02arm: Fix stage 2 memory attribute checking in AArch64Dylan Johnson
Change-Id: I14c93a5460550051a12129e792a9a9bd522a145c
2016-08-02arm: Fix trapping to Hypervisor during MSR/MRS read/writeDylan Johnson
This patch restricts trapping to hypervisor only if we are in the correct exception level for the trap to happen. Change-Id: I0a382b6a572ef835ea36d2702b8a81b633bd3df0
2016-08-02arm: Fix secure state checking in various placesDylan Johnson
Faults that could potentially be routed to the hypervisor checked whether or not they were in a secure state without checking if security was enabled or not. This caused faults not to be routed correctly. This patch causes secure state checking to first ask if security is enabled. Change-Id: I179e9b181b27f552734c9bab2b18d05ac579a119
2016-08-02arm: Fix stage 2 determination in table walkerDylan Johnson
We recompute if we are doing a stage 2 walk inside of the table walker but we have already figured it out in the tlb. Pass the information in to the walk instead of recomputing it. Change-Id: I39637ce99309b2ddbc30344d45ac9ebf6a203401
2016-08-02arm: Refactor aarch64 table walk logic to remove redundancyDylan Johnson
The functional case is already handled within the fetchDescriptor() function. We can thus use that function for both atomic and functional mode when we start the table walk. Change-Id: Iacaed28cd9024d259fd37a58150efd00ff94d86e
2016-08-02arm: Add check to fault routing for hypervisor/virtualizationDylan Johnson
This patch adds the option for faults to be routed to the hypervisor using the pre-existing routeToHyp() functions that are present in each fault type. Change-Id: I9735512c094457636b9870456a5be5432288e004
2016-08-02arm: Fix EL perceived at TLB for address translation instructionsDylan Johnson
During address translation instructions (such as AT S1E1R_Xt) the exception level can be different than the current exception level. This patch fixes how the TLB determines what EL to use during these instructions. Change-Id: Ia9ce229404de9e284bc1f7479fd2c580efd55f8f
2016-08-02arm: Add AArch64 hypervisor call instruction 'hvc'Dylan Johnson
This patch adds the AArch64 instruction hvc which raises an exception from EL1 into EL2. The host OS uses this instruction to world switch into the guest. Change-Id: I930ee43f4f0abd4b35a68eb2a72e44e3ea6570be
2016-08-02arm: add stage2 translation supportDylan Johnson
Change-Id: I8f7c09c7ec3a97149ebebf4b21471b244e6cecc1
2016-08-02arm: enable EL2 supportCurtis Dunham
Change-Id: I59fa4fae98c33d9e5c2185382e1411911d27d341
2016-08-02arm: invalidate TLB miscreg cache on modification of HSCTLRDylan Johnson
Change-Id: I5212c91c56435fe008950ed99feacc6921609226
2016-08-02arm: change instruction classes to catch hyp trapsDylan Johnson
Change-Id: I122918d0e3dfd01ae1a4ca4f19240a069115c8b7
2016-07-22tests: Add regex-based ignore rules for ref filesAndreas Sandberg
There are cases where we need to ignore files with specific extensions (e.g., when Mercurial litters the file system with patch rejects). Implement this functionality using a helper class (FileIgnoreList) that supports both regular expressions and basic string comparisons. Change-Id: I34549754bd2e10ed230ffb2dc057403349f8fa78 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-07-21stats: update referencesCurtis Dunham
2016-07-21arm, config: Add an example ARM big.LITTLE(tm) configuration scriptGabor Dozsa
An ARM big.LITTLE system consists of two cpu clusters: the big CPUs are typically complex out-of-order cores and the little CPUs are simpler in-order ones. The fs_bigLITTLE.py script can run a full system simulation with various number of big and little cores and cache hierarchy. The commit also includes two example device tree files for booting Linux on the bigLITTLE system. Change-Id: I6396fb3b2d8f27049ccae49d8666d643b66c088b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2016-07-21cpu: Fix Minor SMT WFI/drain interaction issuesMitch Hayenga
The behavior of WFI is to cause minor to cease evaluating pipeline logic until an interrupt is observed, however a user may wish to drain the system while a core is sleeping due to a WFI. This patch makes WFI drain. If an actual drain occurs during a WFI, the CPU is already drained and will immediately be ready for swapping, checkpointing, etc. This should not negatively impact performance as WFI instructions are 'stream-changing' (treated like unpredicted branches), so all remaining instructions are wrong-path and will be squashed rapidly. Change-Id: I63833d5acb53d8dde78f9f0c9611de0ece385e45
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