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--HG--
extra : convert_revision : a6cf77f6c902e5f4f0a96206093d123eec2e0167
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dev/ide_disk.cc:
dev/ide_disk.hh:
Add in stats.
sim/stat_control.cc:
sim/stat_control.hh:
Allow setup event to be called with a specific queue.
--HG--
extra : convert_revision : 9310b132b70f967a198cb2e646433f3a5332671e
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--HG--
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cpu/ozone/front_end.hh:
cpu/ozone/front_end_impl.hh:
cpu/ozone/lw_back_end.hh:
Support latency for Ozone FE and BE.
cpu/ozone/lw_back_end_impl.hh:
Support latency for Ozone FE and BE.
Also fixes for switching out, profiling.
cpu/ozone/lw_lsq.hh:
cpu/ozone/lw_lsq_impl.hh:
Fixes for switching out.
cpu/ozone/simple_params.hh:
Updated parameters.
--HG--
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--HG--
extra : convert_revision : eab02dea68442bd3f8c5d1d16b7f93f43cbda2a5
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cpu/cpu_exec_context.cc:
Be sure to switch over the kernel stats so things don't get messed up. This may lead to weird stats files for sampling runs (detailed stats should be correct, regardless of which kernel stats this is defined on).
cpu/o3/cpu.cc:
Updates for switching out. Also include a bunch of debug info if needed.
cpu/o3/fetch_impl.hh:
Switch out properly.
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
Comment out unused stats (they made the stats file huge).
cpu/o3/lsq_unit.hh:
cpu/o3/lsq_unit_impl.hh:
Add in new stat.
cpu/o3/rename.hh:
Fix up for switching out.
cpu/o3/rename_impl.hh:
Fix up for switching out. Be sure to mark any Misc regs as ready if their renamed inst got squashed from being switched out.
cpu/ozone/cpu_impl.hh:
cpu/simple/cpu.cc:
Switch out fixup.
sim/eventq.hh:
Make CPU switching more immediate.
Also comment out the assertion, as it doesn't apply if we're putting it on an inst-based queue.
--HG--
extra : convert_revision : f40ed40604738993f061e0c628810ff37a920562
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cpu/checker/cpu.cc:
Print better error messages.
cpu/checker/cpu.hh:
Fix up small bug (similar to Ozone's DynInsts with FPs and float/doubles), output better messages.
--HG--
extra : convert_revision : 0e199b3dbbcdb5917cdfbebb4c5c18e4b9056c86
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cpu/base.cc:
Be sure to deschedule the profile event so it doesn't take profiles while the CPU is switched out.
Also include the option to reset stats at a specific instruction.
cpu/base.hh:
Include the option to reset stats at a specific instruction.
cpu/checker/cpu_builder.cc:
Handle stats reset inst.
cpu/o3/alpha_cpu_builder.cc:
Handle stats reset inst, allow for profiling.
cpu/ozone/cpu_builder.cc:
Handle profiling, stats reset event, slightly different parameters.
python/m5/objects/BaseCPU.py:
Add in stats reset.
--HG--
extra : convert_revision : e27a78f7fb8fd19c53d9f2c1e6edce4a98cbafdb
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arch/alpha/freebsd/system.cc:
arch/alpha/isa/decoder.isa:
arch/alpha/linux/system.cc:
arch/alpha/system.cc:
arch/alpha/tru64/system.cc:
Let symbol files be read in so that profiling can happen on the binaries as well.
python/m5/objects/System.py:
Add in symbol files.
sim/pseudo_inst.cc:
Load in a specified symbol file.
sim/pseudo_inst.hh:
Allow for symbols to be loaded.
sim/system.hh:
Support symbol file.
util/m5/m5.c:
util/m5/m5op.S:
Add support to m5 util for loading symbols (and readfile).
--HG--
extra : convert_revision : f10c1049bcd7b22b98c73052c0666b964aff222b
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configs/boot/micro_memlat.rcS:
Update these scripts so they work (not sure why they broke)
configs/boot/micro_tlblat.rcS:
Update this script to use a different test.
--HG--
extra : convert_revision : 6e8692540a9fac6ae8f2d9975c70d4135354b849
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arch/alpha/isa_traits.hh:
Add in clear functions.
cpu/base.cc:
cpu/base.hh:
Add in CPU progress event.
cpu/base_dyn_inst.hh:
Mimic normal registers in terms of writing/reading floats.
cpu/checker/cpu.cc:
cpu/checker/cpu.hh:
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
Fix up stuff.
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
Bring up to speed with newmem.
cpu/o3/alpha_cpu_builder.cc:
Allow for progress intervals.
cpu/o3/tournament_pred.cc:
Fix up predictor.
cpu/o3/tournament_pred.hh:
cpu/ozone/cpu.hh:
cpu/ozone/cpu_impl.hh:
cpu/simple/cpu.cc:
Fixes.
cpu/ozone/cpu_builder.cc:
Allow progress interval.
cpu/ozone/front_end_impl.hh:
Comment out this message.
cpu/ozone/lw_back_end_impl.hh:
Remove this.
python/m5/objects/BaseCPU.py:
Add progress interval.
python/m5/objects/Root.py:
Allow for stat reset.
sim/serialize.cc:
sim/stat_control.cc:
Add in stats reset.
--HG--
extra : convert_revision : fdb5ac5542099173cc30c40ea93372a065534b5e
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arch/alpha/isa/decoder.isa:
Marked a few more instructions as unverifiable.
arch/alpha/isa/mem.isa:
Warn instead of panic, otherwise this can cause the simulation to fail even if the instruction is never committed.
--HG--
extra : convert_revision : 12befc6fedd1a6883d0517e649ad01b91fb561ae
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little better.
Also add the option for the checker to update itself with the main CPU's state if it executes an instruction differently (so it will handle DMA timing errors properly).
--HG--
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--HG--
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arch/alpha/ev5.cc:
Update for copying IPRs.
arch/alpha/isa_traits.hh:
Allow for misc register file to serialize. Also add some register copying code.
cpu/cpu_exec_context.cc:
Use ISA's function to copy registers.
--HG--
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--HG--
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--HG--
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--HG--
extra : convert_revision : 3e4df934478de1ef6a84f193d9ef722157ac6baf
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cpu/activity.cc:
cpu/activity.hh:
cpu/o3/alpha_cpu.hh:
Updates to include comments.
cpu/base_dyn_inst.cc:
Remove call to thread->misspeculating(), as it's never actually misspeculating.
--HG--
extra : convert_revision : 86574d684770fac9b480475acca048ea418cdac3
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into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-o3
--HG--
extra : convert_revision : d3381ee4907c2b6f1747c4496c980e34913e81e7
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--HG--
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--HG--
extra : convert_revision : 6c42350fc3cebb5cf4a6da8ea0c51cca15b3f99f
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supports both local and tournament predictors.
cpu/o3/2bit_local_pred.cc:
Branch predictor cleanup/fixup. Rename this to LocalBP.
cpu/o3/2bit_local_pred.hh:
Rename to LocalBP, update to support changes to BPredUnit, include comments.
cpu/o3/alpha_cpu_builder.cc:
Support extra parameters to the branch predictor. Now it takes in a parameter to tell it which branch predictor it is using, the local or the tournament predictor.
cpu/o3/alpha_params.hh:
Add in extra parameter for the branch predictor type.
cpu/o3/bpred_unit.cc:
Branch predictor fixup/cleanup. Rename it to BPredUnit.
cpu/o3/bpred_unit.hh:
Branch predictor fixup/cleanup. Now supports both the local and tournament predictors, and stores the branch predictor update state.
cpu/o3/bpred_unit_impl.hh:
Branch predictor overhaul. Now supports both the local and tournament predictors.
cpu/o3/cpu_policy.hh:
cpu/ozone/ozone_impl.hh:
cpu/ozone/simple_impl.hh:
Reflect the class name change.
cpu/o3/decode_impl.hh:
Be sure to set the predicted target as well so we don't squash twice.
cpu/o3/tournament_pred.cc:
cpu/o3/tournament_pred.hh:
Fixes to the tournament predictor.
cpu/ozone/simple_params.hh:
Include parameter for the branch predictor type.
python/m5/objects/AlphaFullCPU.py:
python/m5/objects/OzoneCPU.py:
Include the parameter for the branch predictor type.
--HG--
extra : convert_revision : 34afebb3b40b47accb12558e439ee4cb03df5e64
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--HG--
extra : convert_revision : aa222dd95d833b16b0f474ec156bd6955c2c54c6
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arch/alpha/ev5.cc:
Fix up some stuff I missed in the last kernel stats checkin.
cpu/checker/cpu.cc:
Allow the checker to disable its kernel stats.
cpu/cpu_exec_context.cc:
Allow CPUExecContext to be created without kernelStats.
cpu/cpu_exec_context.hh:
Allow CPUExecContext to be created without kernelStats. Default usage leaves kernelStats on.
--HG--
extra : convert_revision : 8ed5bffd3a5b6275baa07fb4ea385eeab1a0456a
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cpu/ozone/front_end_impl.hh:
cpu/ozone/lw_back_end_impl.hh:
cpu/ozone/lw_lsq_impl.hh:
Support new flags added in.
--HG--
extra : convert_revision : 2e756fd1913cf600650afc39dd715d59b9b89c42
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into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-o3
--HG--
extra : convert_revision : 804302a5edb9d908808861f7f54a4f3cbb22830c
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arch/alpha/isa/main.isa:
Use automatic path includes thanks to updates to isa parser.
arch/isa_parser.py:
Pull changes to isa parser from newmem into m5. This fixes a bug where the files include in main.isa were not being included as dependencies properly.
--HG--
extra : convert_revision : 8ef1e2e1a64e7a5762baf7a09abc8665d7c2f688
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into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-o3
--HG--
extra : convert_revision : 0a6140f3f5e7c454981c5aa2b221224f076e50eb
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The "execute" portion of IEW is really just the last cycle of execution, at which point execute() gets called. Execution begins inside the IQ, when it schedules FUs for specific instructions. As a result, the Execute stage should just pull all completing instructions out of the IQ stage and execute them.
Limiting the number of writebacks outstanding must still be done.
cpu/o3/iew_impl.hh:
Rework how instructions are scheduled and executed. There shouldn't be a specific "width" from issue to execute because issue does the scheduling of the functional units (really the beginning of the execution).
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
Rework how instructions are scheduled and executed.
--HG--
extra : convert_revision : bbf1a8a4c0a2f2a938bdd78d74493048fd3b4b55
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cpu/checker/cpu.cc:
Cleanup checker, give more useful warning messages.
Also fix bug
cpu/checker/cpu.hh:
Cleanup checker, use forward declaration instead of include.
--HG--
extra : convert_revision : 8f231199a0a75788218320cdbcc7f70441e5d574
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cpu/base_dyn_inst.hh:
Code cleanup
--HG--
extra : convert_revision : 501c03f8e4346ffbcb545ddeee30c1f8ded9baa7
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arch/alpha/ev5.cc:
Move kernel stats out of CPU and into XC. Also be sure to check if the kernel stats exist prior to using them.
--HG--
extra : convert_revision : 565cd7026410fd7d8586f953d9b328c2e67a9473
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IsIprAccess flag may go away in the future (op class can be used to tell this), and the CPU still needs a specific way to identify/deal with syscalls.
arch/alpha/isa/decoder.isa:
Added a few extra flags to help the new CPU identify various classes of instructions without having to force certain behaviors for all CPUs.
cpu/base_dyn_inst.hh:
cpu/static_inst.hh:
Added extra flags.
cpu/o3/iew_impl.hh:
cpu/o3/inst_queue_impl.hh:
Handle store conditionals specially.
cpu/o3/lsq_unit_impl.hh:
Extra flags tells if the instruction is a store conditional.
cpu/o3/rename_impl.hh:
Handle IPR accesses and store conditionals specially.
--HG--
extra : convert_revision : 39debec4fa5341ae8a8ab5650bd12730aeb6c04f
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regressions.
This temporarily will break the O3 and Ozone CPU models. Updates to fix them will be coming soon.
arch/alpha/isa/decoder.isa:
Undo changes to instruction flags that has caused statistics to change in regressions.
--HG--
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--HG--
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cpu/o3/commit_impl.hh:
O3 code update/cleanup. Fetch fault code no longer needed (see previous checkin).
--HG--
extra : convert_revision : f602e7f978e19b8900dce482f38f9c7a195e94da
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cpu/SConscript:
Remove sat_counter.cc and push its functions into the .hh file (all functions were 3 or less lines).
cpu/o3/sat_counter.hh:
Incorporate .cc code into this file.
--HG--
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--HG--
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Dependecy graph code moved into its own class.
This requires the changes to the functional units, which is in the next check in.
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
IEW and IQ code cleanup and reorganization.
cpu/o3/inst_queue.cc:
Dependency graph code moved into its own class now.
cpu/o3/inst_queue.hh:
IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
cpu/o3/inst_queue_impl.hh:
IEW/IQ code cleanup and reorganization.
Dependecy graph code moved into its own class.
Issue loop cleaned up, with completion events for functional units now used more correctly (before they weren't used for multi-cycle ops with pipelined FU's).
--HG--
extra : convert_revision : 35e50192df6f71dc81d46a73fdd65f7ec07c10e4
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to keep track of the activity tracking internals; it just calls advance() on the class and uses it to tell if it should deschedule itself.
SConscript:
Split off activity/idling code into its own class to do the processing separately.
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_params.hh:
Activity stuff. This is mostly for debugging and may be removed later on (or changed to enable/disable activity idling).
cpu/o3/cpu.cc:
Move activity idling stuff mostly into its own class, so it no longer clutters this file.
cpu/o3/cpu.hh:
Move activity idling stuff into its own class.
python/m5/objects/AlphaFullCPU.py:
Add parameter for initial activity value.
--HG--
extra : convert_revision : f32f7cc03895dc07ab57ddba78c5402a1a8b0f1a
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--HG--
extra : convert_revision : 1f59c853cb0e327d7cf586021b5139f1242e4f28
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instruction and giving it the fault. This unifies front end faults and normal instruction faults.
cpu/checker/cpu.cc:
Fixups for fetch fault being sent with the instruction.
cpu/o3/fetch_impl.hh:
cpu/ozone/front_end_impl.hh:
Send any faults generated at fetch along with a fake nop instruction to the back end. This avoids having to use direct communication to check if the entire front end has drained; it is naturally handled through the nop's fault being handled when it reaches the head of commit.
cpu/ozone/front_end.hh:
Add extra status TrapPending.
cpu/ozone/lw_back_end_impl.hh:
Fetch fault handled through a dummy nop carrying the fetch fault.
Avoid putting Nops on the exeList.
--HG--
extra : convert_revision : 8d9899748b34c204763a49c48a9b5113864f5789
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scons 0.96.9* versions.
arch/SConscript:
Backport ISA scanner fix from newmem.
--HG--
extra : convert_revision : 96be75660f85900fd26badef36fb4109b36d8394
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into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-merge
--HG--
extra : convert_revision : 077a04edf0e3e4d735e88c9741d6742666e97de6
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--HG--
extra : convert_revision : f733bc68758d95987dfc481d48a4623c23b16ede
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into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-merge
--HG--
extra : convert_revision : 182df443376e5561d46f323d36089a2a49dc2024
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--HG--
extra : convert_revision : 148c59f430874e8425952db6960ca4f5e57e2a42
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cpu/ozone/cpu.hh:
Updates for sampler.
cpu/ozone/cpu_impl.hh:
Updates for sampler, checker.
cpu/ozone/inorder_back_end.hh:
Sampler updates. Also support old memory system.
--HG--
extra : convert_revision : 33ebe38e4c08d49c6af84032b819533b784b4fe8
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cpu/o3/alpha_cpu.hh:
Update for sampler to work properly. Also code cleanup.
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_dyn_inst.hh:
Updates to support the checker.
cpu/o3/alpha_cpu_impl.hh:
Updates to support the checker. Also general code cleanup.
cpu/o3/alpha_dyn_inst_impl.hh:
Code cleanup.
cpu/o3/alpha_params.hh:
Updates to support the checker. Also supports trap latencies set through the parameters.
cpu/o3/commit.hh:
Supports sampler, checker. Code cleanup.
cpu/o3/commit_impl.hh:
Updates to support the sampler and checker, as well as general code cleanup.
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
Support sampler and checker.
cpu/o3/decode_impl.hh:
Supports sampler.
cpu/o3/fetch.hh:
Supports sampler. Also update to hold the youngest valid SN fetch has seen to ensure that the entire pipeline has been drained.
cpu/o3/fetch_impl.hh:
Sampler updates. Also be sure to not fetches to uncached space (bad path).
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
Sampler updates.
cpu/o3/lsq_unit_impl.hh:
Supports checker.
cpu/o3/regfile.hh:
No need for accessing xcProxies directly.
cpu/o3/rename.hh:
cpu/o3/rename_impl.hh:
Sampler support.
--HG--
extra : convert_revision : 03881885dd50ebbca13ef31f31492fd4ef59121c
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