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AgeCommit message (Expand)Author
2011-09-13IGbE: Clean up debug printing and proprly account for copied bytes.Ali Saidi
2011-09-13ARM: update TLB to set request packet ASID fieldDaniel Johnson
2011-09-13Mem: Allow ASID to be set after request is created.Daniel Johnson
2011-09-13CP15 c15: enable execution with accesses to c15 registersChander Sudanthi
2011-09-13ARM: Implement numcpus bits in L2CTLR register.Daniel Johnson
2011-09-13Prefetch: Don't prefetch if address is in the write queue.Ali Saidi
2011-09-13gem5ops: Implement Java JNI for gem5OpsPrakash Ramrakhyani
2011-09-13O3: Update stats for new ordering fix.Ali Saidi
2011-09-13LSQ: Only trigger a memory violation with a load/load if the value changes.Ali Saidi
2011-09-10MIPS: Implement gem5/src/arch/mips/remote_gdb.cc.Deyuan Guo
2011-09-10PseudoInst: Add compiler guards to pseudo_inst.hh.Gabe Black
2011-09-09StaticInst: Merge StaticInst and StaticInstBase.Gabe Black
2011-09-09Decode: Pull instruction decoding out of the StaticInst class into its own.Gabe Black
2011-09-09MIPS: Update MIPS stats for cleaned up operand checks.Gabe Black
2011-09-09Stack: Tidy up some comments, a warning, and make stack extension consistent.Gabe Black
2011-09-08ISA parser: Don't look for operands in strings.Gabe Black
2011-09-08ISA parser: Match /* */ and // style comments.Gabe Black
2011-09-05X86: Make sure instruction flags are set properly even on 32 bit machines.Gabe Black
2011-09-05X86,TLB: Make sure the "delayedResponse" variable is always set.Gabe Black
2011-09-02TLB: comments and a helpful warning.Lisa Hsu
2011-09-01Fix build for gcc-4.2 opt/fastLisa Hsu
2011-09-01Functional Accesses: Update states to support Broadcast/Snooping protocols.Lisa Hsu
2011-08-29SLICC: Pass arguments by referenceNilay Vaish
2011-08-29Ruby: Remove some unused codeNilay Vaish
2011-08-26Ruby: Eliminate modulo op for computing set size.Nilay Vaish
2011-08-19ARM: Add some MP regressions and clean up the disk images and kernels a bitAli Saidi
2011-08-19ARM: Mark some variables uncacheable until boot all CPUs are enabled.Ali Saidi
2011-08-19Mem: Put prefetcher notify call before packet is deleted.Ali Saidi
2011-08-19ARM: Add VExpress_E support with PCIe to gem5Ali Saidi
2011-08-19ARM: Add support for Versatile Express boardsAli Saidi
2011-08-19ARM: Make GIC function that should only be called by GIC protected.Ali Saidi
2011-08-19IDE: Fix issues with new PIIX kernel driver and our model.Ali Saidi
2011-08-19StoreSet: Update stats for store-set clearingAli Saidi
2011-08-19ARM: Add support for DIV/SDIV instructions.Ali Saidi
2011-08-19LSQ: Set store predictor to periodically clear itself as recommended in the s...Ali Saidi
2011-08-19Fix bugs due to interaction between SEV instructions and O3 pipelineGeoffrey Blake
2011-08-19O3: Update stats for LSQ changes.Ali Saidi
2011-08-19LSQ: Add some better dprintfs for storeset predictor.Mrinmoy Ghosh
2011-08-19LSQ: Fix a few issues with the storeset predictor.Mrinmoy Ghosh
2011-08-19Stats: Add a sparse histogram stat object.Thomas Grass
2011-08-19O3: Squash the violator and younger instructions instead not all insts.Giacomo Gabrielli
2011-08-19ARM: Add per-cpu local timers for ARM.Geoffrey Blake
2011-08-19ARM: Add per-processor interrupt support to GIC.Prakash Ramrakhani
2011-08-19ARM: Fix a memory leak with the table walker.Ali Saidi
2011-08-19Prefetcher: Fix some memory leaks with the prefetcher.Ali Saidi
2011-08-19ARM: quiet what can be a very noise CLCD controller.Ali Saidi
2011-08-16InOrder: Make cache_unit.hh include hashmap.hh explicitly, not transitively.Gabe Black
2011-08-16O3: Make lsq_unit.hh include arch/isa_traits.hh directly, not transitively.Gabe Black
2011-08-15Ruby: Initialize some variables.Nilay Vaish
2011-08-14X86: Add an X86_FS o3 regression.Gabe Black