Age | Commit message (Collapse) | Author |
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extra : convert_revision : db9a526bddc8634cea63b42b882f580806066db5
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extra : convert_revision : d29efe01781d72ee6e61818e7b93972262c0616b
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register numbers correlate to the numbers used in SPARC in m5 and statetrace.
src/cpu/exetrace.cc:
Fixed up to deal with microcode, and to make floating point register numbers correlate to the numbers used in SPARC.
util/statetrace/arch/tracechild_sparc.cc:
util/statetrace/arch/tracechild_sparc.hh:
Make floating point register numbers correlate to the numbers used in SPARC.
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calculation.
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extra : convert_revision : 0202e130b170dcc2f45403c58cf51ec8c2e4e094
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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extra : convert_revision : 898976bbd322e55bc234035456df8090c6dcf72d
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src/arch/sparc/isa/formats/blockmem.isa:
Several small and medium bug fixes.
src/cpu/simple/base.cc:
Fixed a few compiler errors and made sure the next micro pc is set to 1 to prevent the first microop from executing twice. Also fixed a fetching bug.
src/cpu/thread_state.cc:
Made sure the microPC and nextMicroPC are initialized properly.
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since otherwise the EXT_ASI field is lost.
src/arch/sparc/isa/base.isa:
src/arch/sparc/isa/formats/micro.isa:
Switch MachInst to ExtMachInst so that the EXT_ASI field is available to the instructions.
src/arch/sparc/utility.hh:
Made sure EXT_ASI was set to the appropriate ASI value whether or not the asi register was used.
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are not processed as code.
src/arch/isa_parser.py:
Changed the way the extra template parameters are specified. MIPS might need to be adjusted.
src/arch/sparc/isa/decoder.isa:
Changed how Frd_N was set up.
src/arch/sparc/isa/formats/blockmem.isa:
Fixed up handling of block memory operations
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem.isa:
src/arch/sparc/isa/formats/priv.isa:
Fix up extra template parameters.
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem_bus
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but I believe it should fix what she's running into (which was definitely a bug).
src/cpu/o3/fetch_impl.hh:
Move assertion to area where it should really always be true. Sometimes you might recvRetry and not necessarily be blocked (if there was a squash).
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extra : convert_revision : 76ad35357e7f4c44fa544ffed071096a62053018
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extra : convert_revision : cd0d13a85ddc7599308db8604a8f63a48679cc05
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
src/cpu/simple/timing.cc:
hand merge
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extra : convert_revision : 083bf102249ad9bc63c447dbf85d3863f935f647
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relied on implementation specific behavior, namely right shifting a signed value.
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extra : convert_revision : 4f5ef44d012de87919ad681024fe2ed0213a412f
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src/arch/sparc/isa/bitfields.isa:
Added a field to retrieve the asi from the ExtMachInst
src/arch/sparc/isa/decoder.isa:
Fixed up how the size of memory operations where handled, and use the new EXT_ASI bit field.
src/arch/sparc/isa/formats.isa:
add includes for the new formats.
src/arch/sparc/isa/formats/basic.isa:
Add a template for BasicDecodeWithMnemonic which is needed by the unimp format.
src/arch/sparc/isa/formats/mem.isa:
Change around the memory format to figure out the memory access width on its own.
src/arch/sparc/isa/operands.isa:
Added support for the operands of block loads/stores which are offset from Frd.
src/arch/sparc/utility.hh:
Encoded the ASI into the ExtMachInst
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This takes advantage of microcode.
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Alpha
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extra : convert_revision : 7e26053696b23fbc0b8cd5827a5072dcf2526e2b
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fixPacket() should be used anywhere a functional packet and timing packet are found to have the same address.
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extra : convert_revision : 783ec438271b24ddb0ae742b4efd1ed7d6be93f3
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into zooks.eecs.umich.edu:/y/ksewell/research/m5-sim/cleanrepo
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into zeep.pool:/z/saidi/work/m5.newmem.head
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extra : convert_revision : 0e184a0784100112db5841c587bd3dd638f8bdc0
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into zooks.eecs.umich.edu:/y/ksewell/research/m5-sim/cleanrepo
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : fa5b2cfa79d87a0612b8116d407a8b2959d9095a
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src/mem/cache/base_cache.hh:
Remove top level param from cache
src/mem/cache/coherence/uni_coherence.cc:
Remove top level parameters from the cache
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extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0
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into zeep.pool:/z/saidi/work/m5.newmem.head
src/mem/packet.hh:
hand merge
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extra : convert_revision : 3f77707360235dc98c6b12a0367ca64a401313df
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implement fix packet and add the ability to print a packet to a ostream
remove tabs in packet.hh (Could people stop inserting them??!?!?!)
mark const functions in packet.hh as such
src/base/traceflags.py:
add a traceflag for functional accesses
src/mem/packet.cc:
implement fix packet and add the ability to print a packet to a ostream
src/mem/packet.hh:
add the ability to print a packet to an ostream
remove tabs in file
mark const functions as such
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extra : convert_revision : 4297bce5e1d3abbab48be5bd9eb9e982b751fc7c
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The response queue is not tying up an MSHR, should we change that or assume infinite storage for responses?
src/mem/cache/base_cache.cc:
src/mem/tport.cc:
Add in functional check of retry queued packets.
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extra : convert_revision : 0cb40b3a96d37a5e9eec95312d660ec6a9ce526a
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src/cpu/memtest/memtest.cc:
Another memleak in the memtester
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src/base/traceflags.py:
src/mem/physical.cc:
Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
Set the size properly on unCacheable accesses
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extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : b6224624ea493531e5ecc161bede7433f96d8a0f
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Fix a segfault associated with DefaultId
src/mem/bus.cc:
Handle a segfault in the bus when DefaultPort was being used
src/mem/bus.hh:
Make the Default ID more unique (it overlapped with Broadcast ID)
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src/mem/bus.cc:
Add debugging statement
src/mem/bus.hh:
Fix implementation of bus for subsequent recvTimings while handling a retry request.
src/mem/tport.cc:
Rework timing port to retry properly
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