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AgeCommit message (Expand)Author
2014-01-04ruby: remove cntrl_id from python config scripts.Nilay Vaish
2014-01-04ruby: add support for clustersNilay Vaish
2014-01-04ruby: some small changesNilay Vaish
2014-01-03config, x86: move kernel specification from tests to FSConfig.pySteve Reinhardt
2014-01-03python: provide better error message for wrapped C++ methodsSteve Reinhardt
2014-01-03python: don't die on assignment to cloned objectSteve Reinhardt
2013-12-29sim: Add support for dynamic frequency scalingChristopher Torng
2013-12-29mips: Floating point convert bug fixChristopher Torng
2013-12-26stats: updates due to bug fixed in mesi coherence protocolNilay Vaish
2013-12-26ruby: fix bugs in mesi cmp directory protocolNilay Vaish
2013-12-20ruby: slicc: replace max_in_port_rank with number of inportsNilay Vaish
2013-12-20ruby: declare variables to be unsigned in Address.hhNilay Vaish
2013-12-20ruby: mesi: remove owner and sharer fields from directory tagsNilay Vaish
2013-12-03sim: reset stats after startupNilay Vaish
2013-12-03cpu: call BaseCPU startup() function in o3 cpuNilay Vaish
2013-12-03util: update checkpoint aggregation scriptNilay Vaish
2013-11-29base: Fix race in PollQueue and remove SIGALRM workaroundAndreas Sandberg
2013-11-29base: Clean up signal handlingAndreas Sandberg
2013-11-26stats: updates due to changes to ticksToCycles()Nilay Vaish
2013-11-26sim: correct ticksToCycles() function.Nilay Vaish
2013-10-15kvm: Set the perf exclude_host attribute if availableAndreas Sandberg
2013-11-26x86: Implementation of Int3 and Int_Ib in long modeChristian Menard
2013-11-26kvm: Remove the unused hostFreq member from BaseKvmCPUAndreas Sandberg
2013-11-25sim: simulate with multiple threads and event queuesSteve Reinhardt ext:(%2C%20Nilay%20Vaish%20%3Cnilay%40cs.wisc.edu%3E%2C%20Ali%20Saidi%20%3CAli.Saidi%40ARM.com%3E)
2013-11-15cpu: allow the fetch buffer to be smaller than a cache lineAnthony Gutierrez
2013-11-15cpu: Fix Checker register index useAndreas Hansson
2013-11-14tests: suppress output on switcheroo testsSteve Reinhardt
2013-11-12sim: fix event priority name for debug-start optionAnthony Gutierrez
2013-11-01stats: Bump stats to match DRAM controller changesAndreas Hansson
2013-11-01mem: Fixes for DRAM stats accountingAndreas Hansson
2013-11-01mem: Fix the LPDDR3 page sizeAndreas Hansson
2013-11-01mem: Adding stats for DRAM power calculationNeha Agarwal
2013-11-01mem: Unify request selection for read and write queuesNeha Agarwal
2013-11-01mem: Add a simple adaptive version of the open-page policyAndreas Hansson
2013-11-01mem: Just-in-time write scheduling in DRAM controllerNeha Agarwal
2013-11-01mem: Add tRRD as a timing parameter for the DRAM controllerAndreas Hansson
2013-11-01mem: Less conservative tRAS in DRAM configurationsAndreas Hansson
2013-11-01mem: Make tXAW enforcement less conservative and per rankAni Udipi
2013-11-01mem: Fix for 100% write threshold in DRAM controllerNeha Agarwal
2013-11-01mem: Pick the next DRAM request based on bank availabilityAndreas Hansson
2013-11-01mem: Use the same timing calculation for DRAM read and writeAni Udipi
2013-11-01mem: Fix DRAM bank occupancy for streaming accessAni Udipi
2013-11-01mem: Schedule time for DRAM event taking tRAS into accountAni Udipi
2013-11-01mem: Add tRAS parameter to the DRAM controller modelAni Udipi
2013-11-01stats: Bump stats after shifting to SimpleMemoryAndreas Hansson
2013-11-01test: Use SimpleMemory for atomic full-system testsAndreas Hansson
2013-11-01sim: Clarify the difference between tracing and debuggingAndreas Hansson
2013-10-31ARM: add support for TEEHBR accessChander Sudanthi
2013-10-31dev: Add 'OSC' oscillator sys control reg support to VersatileExpressMatt Evans
2013-10-31dev: Add support for MSI-X and Capability Lists for ARM and PCI devicesGeoffrey Blake