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2016-04-21mem: Remove unused cache statsAndreas Hansson
Prune cache stats that are never actually used.
2016-04-21mem: Deallocate all write-queue entries when sentAndreas Hansson
This patch removes the write-queue entry tracking previously used for uncacheable writes. The write-queue entry is now deallocated as soon as the packet is sent. As a result we also forego the stats for uncacheable writes. Additionally, there is no longer a need to attach the write-queue entry to the packet.
2016-04-21mem: Align downstream cache packet creation in atomic and timingAndreas Hansson
This patch makes the control flow more uniform in atomic and timing, ultimately making the code easier to understand.
2016-04-21config: Add missing point of coherency to memcheck scriptAndreas Hansson
Bring in line with changes to the XBar class.
2016-04-18scons: Fix Python 2.6 compatibilityAndreas Sandberg
Don't use Python 2.7-style with statements in the SConstruct file.
2016-04-18style: Fix Python 2.6 compatibilityAndreas Sandberg
The style checker code needs to disable autojunk when diffing source files using Python's difflib. Support for this was only introduced in Python 2.7, which leads to a TypeError exception on older Python version. This changeset adds a fallback mechanism for old Python versions.
2016-04-15ruby: Fix block_on behaviorJoel Hestness
Ruby's controller block_on behavior aimed to block MessageBuffer requests into SLICC controllers when a Locked_RMW was in flight. Unfortunately, this functionality only partially works: When non-Locked_RMW memory accesses are issued to the sequencer to an address with an in-flight Locked_RMW, the sequencer may pass those accesses through to the controller. At the controller, a number of incorrect activities can occur depending on the protocol. In MOESI_hammer, for example, an intermediate IFETCH will cause an L1D to L2 transfer, which cannot be serviced, because the block_on functionality blocks the trigger queue, resulting in a deadlock. Further, if an intermediate store arrives (e.g. from a separate SMT thread), the sequencer allows the request through to the controller, and the atomicity of the Locked_RMW may be broken. To avoid these problems, disallow the Sequencer from passing any memory accesses to the controller besides Locked_RMW_Write when a Locked_RMW is in- flight.
2016-04-15arm,dev: remove PMU assertion hit on resetBjoern A. Zeeb
Remve the assertion that we always need to add a delta larger than zero as that does not seem to be true when we hit it in the 'PMU reset cycle counter to zero' case. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-04-15mem: FreeBSD does not provide MAP_NORESERVE eitherBjoern A. Zeeb
Like OS X, FreeBSD does not support MAP_NORESERVE. Handle accordingly and update comment. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-04-15misc: Bugfix in TLM memInhibit CommandAbdul Mutaal Ahmad
memInhibitAsserted() has been removed from packet.hh. This change has been reflected in TLM based SystemC memory. This patch also adds a number of panics asserting the SystemC memory only sees requests it expects. Committed by Jason Lowe-Power <power.jg@gmail.com>
2016-04-14dist: config file for distributed switchMohammad Alian
Distributed gem5 is the result of the convergence effort between multi-gem5 and pd-gem5. It relies on the base multi-gem5 infrastructure for packet forwarding, synchronisation and checkpointing but combines those with the elaborated network switch model from pd-gem5.
2016-04-13misc: Fix issues flagged by gcc 6Andreas Hansson
A few warnings (and thus errors) pop up after being added to -Wall: 1. -Wmisleading-indentation In the auto-generated code there were instances of if/else blocks that were not indented to gcc's liking. This is addressed by adding braces. 2. -Wshift-negative-value gcc is clever enougn to consider ~0 a negative constant, and rightfully complains. This is addressed by using mask() which explicitly casts to unsigned before shifting. That is all. Porting done.
2016-04-12misc: Appease clang...againAndreas Hansson
Once again, clang is having issues with recently committed code. Unfortunately HSAIL_X86 is still broken.
2016-04-09stats: Match current behaviourAndreas Hansson
Small changes to the branch predictor and BTB caused stats changes throughout.
2016-04-08stats: update stats for thermals, indirect BPCurtis Dunham
2016-04-07mem: Add priority to QueuedPrefetcherRekai Gonzalez Alberquilla
Queued prefetcher entries now count with a priority field. The idea is to add packets ordered by priority and then by age. For the existing algorithms in which priority doesn't make sense, it is set to 0 for all deferred packets in the queue.
2016-04-07mem: Handful extra features for BasePrefetcherRekai Gonzalez Alberquilla
Some common functionality added to the base prefetcher, mainly dealing with extracting the block address, page address, block index inside the page and some other information that can be inferred from the block address. This is used for some prefetching algorithms, and having the methods in the base, as well as the block size and other information is the sensible way.
2016-04-07mem: Add Program Counter to MemTraceProbeVictor Garcia
2015-05-27mem: Add unused prefetch counter in cachesRekai Gonzalez Alberquilla
Added stat to the cache to account for HardPF'ed blocks that are evicted before being referenced (over-prefetching).
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu. This is a re-spin of 20264eb after the revert (bd1c6789) and includes some fixes of that commit.
2016-04-05cpu: Implement per-thread GHRsMitch Hayenga
Branch predictors that use GHRs should index them on a per-thread basis. This makes that so. This is a re-spin of fb51231 after the revert (bd1c6789).
2016-04-05cpu: Add an indirect branch target predictorMitch Hayenga
This patch adds a configurable indirect branch predictor that can be indexed by a combination of GHR and path history hashes. Implements the functionality described in: "Target prediction for indirect jumps" by Chang, Hao, and Patt http://dl.acm.org/citation.cfm?id=264209 This is a re-spin of fb9d142 after the revert (bd1c6789).
2016-04-05cpu: Fix BTB threading oversightMitch Hayenga
The extant BTB code doesn't hash on the thread id but does check the thread id for 'btb hits'. This results in 1-thread of a multi-threaded workload taking a BTB entry, and all other threads missing for the same branch missing.
2016-04-06misc: Bail out of DVFS dot if we cannot resolve the domainsSascha Bischoff
This changeset updates the dot output to bail out if it is unable to resolve the voltage or clock domains (which will cause it to raise an AttributeError). Additionally, the DVFS dot output is disabled by default for speed purposes. Minor fixup for 0aeca8f.
2016-04-07Revert to 74c1e6513bd0 (sim: Thermal support for Linux)Andreas Sandberg
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
The following patches had unexpected interactions with the current upstream code and have been reverted for now: e07fd01651f3: power: Add support for power models 831c7f2f9e39: power: Low-power idle power state for idle CPUs 4f749e00b667: power: Add power states to ClockedObject Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> --HG-- extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
In general, the ThreadID parameter is unnecessary in the memory system as the ContextID is what is used for the purposes of locks/wakeups. Since we allocate sequential ContextIDs for each thread on MT-enabled CPUs, ThreadID is unnecessary as the CPUs can identify the requesting thread through sideband info (SenderState / LSQ entries) or ContextID offset from the base ContextID for a cpu.
2016-04-05cpu: Implement per-thread GHRsCurtis Dunham
Branch predictors that use GHRs should index them on a per-thread basis. This makes that so.
2016-04-05cpu: Add an indirect branch target predictorMitch Hayenga
This patch adds a configurable indirect branch predictor that can be indexed by a combination of GHR and path history hashes. Implements the functionality described in: "Target prediction for indirect jumps" by Chang, Hao, and Patt http://dl.acm.org/citation.cfm?id=264209
2016-04-05cpu: Fix BTB threading oversightMitch Hayenga
The extant BTB code doesn't hash on the thread id but does check the thread id for 'btb hits'. This results in 1-thread of a multi-threaded workload taking a BTB entry, and all other threads missing for the same branch missing.
2016-04-05power: Add support for power modelsDavid Guillen Fandos
This patch adds some basic support for power models in gem5. The power interface is defined so it can interact with thermal models as well. It implements a simple power evaluator that can be used for simple power models that express power in the form of a math expression. These expressions can use stats within the same SimObject (or down its hierarchy) and some magic variables such as "temp" for temperature. In future patches we will extend this functionality to allow slightly more complex expressions. The model allows it to be extended to use other kinds of models. Finally, the thermal model is updated to use the power usage as input.
2014-12-09power: Low-power idle power state for idle CPUsAkash Bagdia
Add functionality to the BaseCPU that will put the entire CPU into a low-power idle state whenever all threads in it are idle.
2014-11-18power: Add power states to ClockedObjectAkash Bagdia
Add 4 power states to the ClockedObject, provides necessary access functions to check and update the power state. Default power state is UNDEFINED, it is responsibility of the respective simulation model to provide the startup state and any other logic for state change. Add number of transition stat. Add distribution of time spent in clock gated state. Add power state residency stat. Add dump call back function to allow stats update of distribution and residency stats.
2015-05-13sim: Thermal support for LinuxDavid Guillen Fandos
This patch enables Linux to read the temperature using hwmon infrastructure. In order to use this in your gem5 you need to compile the kernel using the following configs: CONFIG_HWMON=y CONFIG_SENSORS_VEXPRESS=y And a proper dts file (containing an entry such as): dcc { compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; temp@0 { compatible = "arm,vexpress-temp"; arm,vexpress-sysreg,func = <4 0>; label = "DCC"; }; };
2015-05-12sim: Adding thermal model supportDavid Guillen Fandos
This patch adds basic thermal support to gem5. It models energy dissipation through a circuital equivalent, which allows us to use RC networks. This lays down the basic infrastructure to do so, but it does not "work" due to the lack of power models. For now some hardcoded number is used as a PoC. The solver is embedded in the patch.
2016-04-05cpu: Add instruction opclass histogram to minorMitch Hayenga
2015-12-15misc: Add secondary dot output for DVFS domainsSascha Bischoff
This patch adds a secondary dot output file which shows the DVFS domains. This has been done separately for now to avoid cluttering the already existing diagram. Due to the way that the clock domains are assigned to components in gem5, this output must be generated after the C++ objects have been instantiated. This further motivates the need to generate this file separately to the current dot output, and not to replace it entirely.
2015-12-11sim: Add additional debug information when drainingSascha Bischoff
This patch adds some additional information when draining the system which allows the user to debug which SimObject(s) in the system is failing to drain. Only enabled for the builds with tracing enabled and is subject to the Drain debug flag being set at runtime.
2016-04-01sim: Fix clock_domain unserializationSascha Bischoff
This patch addresses an issue with the unserialization of clock domains. Previously, the previous performance level was not restored due to a bug in the code, which detected the post-unserialize update as superfluous. This patch splits the setting of the clock domain into two parts. The original interface of perfLevel is retained, but the actual update takes place in signalPerfLevelUpdate, which is private to the class. The perfLevel method checks that if the new performance level is different to the previous performance level, and will only call signalPerfLevelUpdate if there is a change. Therefore, the performance level is only updated, and voltage domains notified, if there is an actual change. The split functionality allows signalPerfLevelUpdate to be called by startup() to explicitly force an update post unserialization.
2016-04-05cpu: Query CPU for inst executed from PythonGeoffrey Blake
This patch adds the ability for the simulator to query the number of instructions a CPU has executed so far per hw-thread. This can be used to enable more flexible periodic events such as taking checkpoints starting 1s into simulation and X instructions thereafter.
2016-04-01syscall_emul: remove mmapFlagTableSteve Reinhardt
After all this it turns out we don't even use it.
2016-04-01syscall_emul: factor out flag tables into common fileSteve Reinhardt
The openFlagTable and mmapFlagTables for emulated Linux platforms are basically identical, but are specified repetitively for every platform. Use a common file that gets included for each platform so that we only have one copy, making them more consistent and simplifying changes (like adding #ifdefs). In the process, made some minor fixes that slipped through due to previous inconsistencies, and added more #ifdefs to try to fix building on alternative hosts.
2016-03-30misc: Don't build region.py as a PySourceAndreas Sandberg
The style refactor change (style: Refactor the style checker as a Python package) moved region.py from src/python/m5/util/ to util/style/. The SConscript update accidentally got lost in that commit. This commit removes region.py from src/python/SConscript. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> --HG-- extra : amend_source : f69b75bf636dd4a4232af3e10c29f7eaa4d59dc8
2016-03-30arm: Clean up m5ops assembly libraryAndreas Sandberg
The m5ops assembly library contains a lot of repetitive code. This changeset adds two macros, FOREACH_M5OP and FOREACH_M5_ANNOTATION, to m5ops.h that simplify architecture-specific implementations. The ARM and ARMv8 m5op implementations have been updated to use the new macros. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2016-03-30style: Change maximum line length to 79 charactersAndreas Sandberg
The old style guide used to mandate 78 characters as the maximum line length to accommodate traditional diffs on 80-column terminals. This is an uncommon use case and it has therefore been decided (see email thread on gem5-dev [1]) that a maximum length of 79-characters makes more sense. [1] http://comments.gmane.org/gmane.comp.emulators.m5.devel/29789 Signed-off-by: Andreas Sandberg <aandreas.sandberg@arm.com> Reviewed-by: Brandon Potter <brandon.potter@amd.com> --HG-- rename : util/style.py => util/hgstyle.py extra : rebase_source : 63efcc4da2585ef8c323d6f322736f64d71742f8
2016-03-30style: Add a style checker that doesn't depend on MercurialAndreas Sandberg
The current style checker script, hgstyle.py, assumes that it is being run from Mercurial. This means that it depends on the Mercurial Python libraries, which aren't necessarily present if using git. This changeset adds a new style checker script, style.py, that has been designed to be run from the command line. The script has support for detecting which revision control system is used and is able to query both git and Mercurial for changes. This enables the script to operate on modified regions and/or all of the modified files in the repository. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com> --HG-- extra : rebase_source : 2b420aff79d190f32557bc8822518cbc5d93e999
2016-03-30scons: Automatically install the git style hookAndreas Sandberg
Add a check in the main SConscript that installs the git pre-commit hook in util/ if git is used. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> [andreas.sandberg@arm.com: Cleanups suggested by Steve] Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com> --HG-- extra : rebase_source : 4b805cdd74bc5442a65abf8a62e3e341f352c04e
2016-03-30style: Add a git pre-commit hookAndreas Sandberg
Add a git pre-commit hook that verifies that files that are about to be committed. Since git stages changes into an index and the index contains the changes that will be committed, the style checker only looks at the state of files in the index. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com> --HG-- extra : rebase_source : 22a028bf13524cba188bd7896a0304f4c14ffeeb
2016-03-30style: Add repository helper functionsAndreas Sandberg
Add an AbstractRepo class and implementations for git and Mercurial that provide a common interface to query repository status for style checkers. The class defines the interfaces to list modified files that are about to be committed and methods to identify changed regions. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com> --HG-- rename : util/style.py => util/hgstyle.py extra : rebase_source : da1f482a1ecac2b0be437dc400b4a66bd3b301cc
2016-03-30style: Remove style validatorsAndreas Sandberg
Style validators provide a subset of the style verifier functionality and are only exposed through the "hg m5format" command. This functionality seems to be both redundant and unused. Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> --HG-- extra : rebase_source : f4847ac3ddc86f6684565b65a942e04979972a7b