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2017-11-16config: Add low power sweep for DRAMRadhika Jagtap
This change adds a Python script to sweep a few parameters with a goal to trigger transitions to the low power states of the DRAM controller. This script is largely based on the sweep.py but is helpful to study the impact of inter-transaction delay on the behaviour of the DRAM in addition to typical sweep params like stride size, bank utilization and read percent. An idle period is added as the last traffic generator state to target hitting self-refresh. Change-Id: I34380afffbf2de9f4e997dfe9fff5e615e077524 Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5725 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-16ext, mem: Pull DRAMPower SHA 90d6290 and rebaseRadhika Jagtap
This patch syncs the DRAMPower library of gem5 to the external github (https://github.com/ravenrd/DRAMPower). The version pulled in is the commit: 90d6290f802c29b3de9e10233ceee22290907ce6 from 30th Oct. 2016. This change also modifies the DRAM Ctrl interaction with the DRAMPower, due to changes in the lib API in the above version. Previously multiple functions were called to prepare the power lib before calling the function that would calculate the enery. With the new API, these functions are encompassed inside the function to calculate the energy and therefore should now be removed from the DRAM controller. The other key difference is the introduction of a new function called calcWindowEnergy which can be useful for any system that wants to do measurements over intervals. For gem5 DRAM ctrl that means we now need to accumulate the window energy measurements into the total stat. Change-Id: I3570fff2805962e166ff2a1a3217ebf2d5a197fb Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5724 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-16pwr: Enable multiple power models per componentDavid Guillen Fandos
This patch allows the user to specify more than one power model for any given Clocked Object. This is useful and some times necessary to properly model components that have multiple power sources (or subcomponents) but gem5 doesn't model them. The ideal solution would be to have a DictParam to replace the VectorParam so each model can have a name and can be identified in the stats file. Change-Id: I4080a7054a16b56069c44750a7a9ce4e674cdf9d Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5733 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-16arch, arm: Print value being ignored on DummyISA writeSean McGoogan
When ignoring writes to the Dummy ISA device (DummyISADevice), additionally print the value being ignored in the diagnostic. Sometimes it is useful to know exactly what we are dropping ... Change-Id: I9a01623611f0da0aa12b065fbb2031aa27e2c036 Signed-off-by: Sean McGoogan <Sean.McGoogan@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5731 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-16sim: Clocked object debug message updated for clarityTiago Muck
Change-Id: I5bbf36ef21ac14d9edf68ec6766d33f88e84d308 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5729 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-11-16sim: Add an option to load additional kernel objectsAndreas Sandberg
There are cases where it is desirable to load a kernel and a set of additional objects. This can, for example, be useful for testing where the bootstrap code can be loaded from one object (the kernel) and the test proper from another. This changeset adds this functionality by adding a kernel_extras vector parameter to the System class. Object files in this vector are loaded in order after the kernel when running in full system mode. Change-Id: I06f57c6a65a17b02eb4267bed0aa829f21bcfa3b Reviewed-on: https://gem5-review.googlesource.com/5703 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-11-15arch-arm: Dsb instruction shouldn't flush the pipelineGiacomo Travaglini
DSB Instruction shouldn't flush the pipeline, hence the IsSquashAfter attribute will be removed for either the 32 and 64 bit version. Change-Id: I98b2b8bc78aa28445ed1a9b5f34645f8d71616ad Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5363 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-15arch-arm: Writes to DCCMVAC shouldn't flush pipelineGiacomo Travaglini
Writes to DCCMVAC (Data Cache line Clean by VA to PoC) system register shouldn't flush the pipeline as a result of the operation. This addition was wrongly introduced for supporting self-modifying code. Software barriers should be used instead. Change-Id: Idf0c27d2e49ca01be19888ae5523b8f8eaefa7b3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5362 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-15arch-arm: Removing FlushPipe fault, using SquashAfterGiacomo Travaglini
This Patch is removing the FlushPipe ArmFault, which was used for flushing the pipeline in favour of the general IsSquashAfter StaticInstr flag. Using a fault was preventing tracers from tracing barriers like ISB and from adding them to the instruction count Change-Id: I176e9254eca904694f2f611eb486c55e50ec61ff Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5361 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-15arm: Add support for armv8 CRC32 instructionsGiacomo Travaglini
This patch introduces the ARM A32/T32/A64 CRC Instructions, which are mandatory since ARMv8.1. The UNPREDICTABLE behaviours are implemented as follows: 1) CRC32(C)X (64 bit) instructions are decoded as Undefined in Aarch32 2) The instructions support predication in Aarch32 3) Using R15(PC) as source/dest operand is permitted in Aarch32 Change-Id: Iaf29b05874e1370c7615da79a07f111ded17b6cc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5521 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-14util: Remove support for hg patches in patch creation scriptAndreas Sandberg
Simplify the patch creation helper script by removing support for automatic conversion to Mercurial's patch format. We no longer use Mercurial as a primary repository, so this support is not likely to be needed again. Change-Id: I83f6efb9ccaee9c548b33257a4d6128153750c76 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5162 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-11-14util: Optionally search entire history when listing changesAndreas Sandberg
The helper script to list changes currently only looks at the changes between a branch point and two heads. This helps performance, but sometimes misclassifies changes that exist both in the upstream branch before the branch point and in a feature branch. Such changes should normally not exist, but can be the product of an incorrect rebase. This change adds an option to the helper script to search the entire upstream repo history when determining the set of upstream changes. When this option is provided, the script lists the changes that exist upstream before the branch point and in the feature branch as "Incorrectly rebased changes". Change-Id: I4cb72cea2152c49d0317dc43613be94a0a2de1e5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5161
2017-11-14cpu, probe: Fix elastic trace register dependencyRadhika Jagtap
Change-Id: I017852eac183fac3f914fdb96d7e72a56ea9d682 Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5121 Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-13config: Fix the "script" SysPath functor.Gabe Black
This particular functor looks in the config root, not in the path specified by M5_ROOT like binary and disk. Change-Id: Ib007c36934c65ca9f808e995a2e0c71f0b338788 Reviewed-on: https://gem5-review.googlesource.com/5641 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-13config: Add an Energy param type.Gabe Black
This type expects values in joules (J). Change-Id: I77a3a4f1c19443f573d5fe7a84d5abd954ce1603 Reviewed-on: https://gem5-review.googlesource.com/5625 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-13config: Export the "Current" param type from m5.params.Gabe Black
This type was defined, but it was never added to __all__. Change-Id: I5414829a9562790416f5ceab71af01503d142903 Reviewed-on: https://gem5-review.googlesource.com/5624 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-13util: Add a "toEnergy" function to the convert module.Gabe Black
Change-Id: I7299af0e2a6ce9bd2272d6ccb898997336e95e51 Reviewed-on: https://gem5-review.googlesource.com/5623 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-13config: Simplify the definitions of the Voltage and Current params.Gabe Black
These had a lot of code which duplicated what was already in the Float param value class. Also, printing into the ini file with "%f" forces python to truncate values which require more precision than the fixed float format supports. Change-Id: Iad9623b71a31d17b69c184082585dcbb881eaa20 Reviewed-on: https://gem5-review.googlesource.com/5622 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-13arch-arm: Interface for the ArmStaticInst intWidth fieldGiacomo Travaglini
ARMv8 Tracers might want to be able to read the intWidth field of the ArmStaticInst object. The field is specifying the bit width of the integer registers used by the current instruction. Change-Id: Iaee3123823a2c7380917001c453377c1c12e54a7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5661 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-13arch-arm: Corrected encoding for T32 HVC instructionGiacomo Travaglini
This patch corrects the encoding of the HVC (Hypervisor Call) for the T32 instruction set. Change-Id: I6f77eaf5c586697e9ccd588419c61e6d90c6c7bf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chuan Zhu <chuan.zhu@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5541 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-11-13util: Simplify/consolidate the python conversion module.Gabe Black
The python conversion module was really repetitive and fragmented, where some types of conversions use common code, and some use hand written case statements which did something very similar. Also, some types like Voltage could only handle V and mV but no other scaling prefix. This change restructures the module to centralize a lot of the unit handling code into toFloat, and makes the various other functions use it. Change-Id: Ic8529203cc226c9b551b8535a444e3f2f25ad1eb Reviewed-on: https://gem5-review.googlesource.com/5621 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-10scons: Move Transform and termcap functionality into their own files.Gabe Black
Change-Id: Ica08e93f3873a7eafd02fe7d44c3bdbf0ce7f6b7 Reviewed-on: https://gem5-review.googlesource.com/5565 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-10scons: Move python path management out of the SConstruct.Gabe Black
Make site_init.py manage sys.path, and the "default" tool set PYTHONPATH on any environment that's created. The paths to add are tracked in a common gem5_python_paths.py. Change-Id: I3387d4394d47a2f9c83322644cfd05909c6890fa Reviewed-on: https://gem5-review.googlesource.com/5564 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-10scons: Pull style hook management out of the main SConstruct.Gabe Black
Put the code which supports style hooks for mercurial and git into two scons "tools". Change-Id: I3ffed85a177be4f9e458fff7b1cf16a3a479914e Reviewed-on: https://gem5-review.googlesource.com/5563 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-10scons: Override the "default" tool to set up the default env.Gabe Black
This imports various environment variables into the scons environment, and sets some general properties on it. These are basically just copied directly from the SConstruct and have the same behavior here. gem5_tool_list will be used later on to add scons "tools" which should be automatically added to new Environment objects. Change-Id: Ib255955090c7b1e1cb80c703c18a9c867fcf1c9e Reviewed-on: https://gem5-review.googlesource.com/5562 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-10scons: Move scons and python version checking into site_init.py.Gabe Black
In an effort to shrink and modularize the main scons files, this change pulls the scons and python version checking code out of the main file and into site_init.py which runs before the SConstruct starts. This will be a place to put really generic code which has to do with the very fundemental aspects of getting scons to work. Other checks, like checks for particular tools or particular versions of tools, will happen in other more specialized files. Change-Id: Icd00ecadbe1141aef4dbadcf42d6ddef1f3a701f Reviewed-on: https://gem5-review.googlesource.com/5561 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-11-09mem: Align the snoop behavior in the XBar for atomic and timingNikos Nikoleris
When the XBar receives a Writeback/WriteClean packet, it doesn't need to snoop the upstream caches. It only queries the snoop filter and sets the blockCached flag accordingly. This is in line with the recvTimingReq. Change-Id: I0ae22f21491d75a111019124bb95bac7b16d3cd3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5043 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-11-09arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1Nikos Nikoleris
A program running in EL0 is allowed to execute CMOs when the UCI bit in SCTLR is set. The execution of dc ivac, however, would fault uncoditionally when executed from EL0. This change aligns the permission checks for dc ivac with the rest of the CMOs. Change-Id: I1a532f37707c7dc0748b4375252c6ec0bbf95419 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5058 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-08dev: Move generic serial devices to src/dev/serialAndreas Sandberg
Change-Id: I104227fc460f8b561e7375b329a541c1fce881b2 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4291 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-11-08dev: Add a dummy serial deviceAndreas Sandberg
Add a dummy serial device that discards any output and doesn't provide any input. This device can be used to terminate UARTs that don't have a default device (e.g., a terminal) attached. Change-Id: I4a6b0b5037ce360f59bfb5c566e1698d113a1d26 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4290 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-11-08dev: Refactor UART->Terminal interfaceAndreas Sandberg
The UART models currently assume that they are always wired to a terminal. While true at the moment, this isn't necessarily a valid assumption. This change introduces the SerialDevice class that defines the interface for serial devices. Currently, Terminal is the only class that implements this interface. Change-Id: I74fefafbbaf5ac1ec0d4ec0b5a0f4b246fdad305 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4289 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-11-07alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates.Gabe Black
In the ISA instruction definitions, some classes were declared with execute, etc., functions outside of the main template because they had CPU specific signatures and would need to be duplicated with each CPU plugged into them. Now that the instructions always just use an ExecContext, there's no reason for those templates to be separate. This change folds those templates together. Change-Id: I13bda247d3d1cc07c0ea06968e48aa5b4aace7fa Reviewed-on: https://gem5-review.googlesource.com/5401 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Alec Roelke <ar4jc@virginia.edu> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-11-06sim-se: Add prlimit system callAlec Roelke
Some ISAs (namely RISC-V) implement getrlimit and setrlimit using prlimit. This patch adds an implementation for the prlimit system call. Normally prlimit is supposed to provide the functionality of both getrlimit and setrlimit, but because gem5 does not support setrlimit this implementation of prlimit will simply display a warning and return a failure code if the setrlimit mode is used. The same thing will happen if a pid other than 0 is passed to it. Change-Id: I653af2d5a60e716f4d6286196be7600409efcef8 Reviewed-on: https://gem5-review.googlesource.com/5321 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-11-02alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.Gabe Black
The ISA parser used to generate different copies of exec functions for each exec context class a particular CPU wanted to use. That's since been changed so that those functions take a pointer to the base ExecContext, so the code which would generate those extra functions can be removed, and some functions which used to be templated on an ExecContext subclass can be untemplated, or minimally less templated. Now that some functions aren't going to be instantiated multiple times with different signatures, there are also opportunities to collapse templates and make many instruction definitions simpler within the parser. Since those changes will be less mechanical, they're left for later changes and will probably be done in smaller increments. Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea Reviewed-on: https://gem5-review.googlesource.com/5381 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-31config: Rework the SysPaths functions into functors.Gabe Black
These functions were already being treated as psuedo objects and had properties assigned to them setting what their paths were. That's a bit unusual and made it less obvious what the code was doing, but also forced the "system" function to know what all the possible path searching functions were so that they'd have their "path" property initialized properly in a central location. This change introduces a PathSearcFunc class which encapsulates the mechanisms of the old code and makes it implicitly extensible so that other path searching functions which might look in other directories can be added in other places. Change-Id: I7be28e51481a06ec83997677af99927709b18003 Reviewed-on: https://gem5-review.googlesource.com/5341 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-31dev: Using Configurable image writer in HDLcdGiacomo Travaglini
The fixed image writer (which was dumping .bmp images only) has been replaced by the configurable one in HDLcd device. Default format is Auto, which gives gem5 the freedom to choose the format it prefers. Change-Id: I0643266556bb10b43cdebd628f6daa2cd5e105dd Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5183 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-31vnc: Default image writer type set to AutoGiacomo Travaglini
This commit modifies the default behaviour of the vnc frame dumping process: rather than using 'Bitmap' as a default parameter value, it is using 'Auto'. Auto parameter is letting gem5 to choose the most efficient image format among the available ones. Change-Id: I3c8e2b5a34a5925d24892880ac362dfe38de36e3 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5182 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-31base: Introducing utility for writing raw data in png formatGiacomo Travaglini
Originally it was possible to use a Bitmap writer class for dumping a framebuffer snapshot in a .bmp file. This patch enables you to choose another format. In particular it implements the writing of PNG Images using libpng library. The latter has to be already installed in your machine, otherwise gem5 will default to the Bitmap format. This configurable writer has been introduced in the VNC frame dumping mechanism, which is storing changed frame buffers from the VNC server Change-Id: Id7e5763c82235f1ce90381c8486b85a7cce734ce Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5181 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-31x86: Fix VEX instruction decoding.Gabe Black
When decoding VEX prefixed instructions, the x86 predecoder wasn't walking past the opcode byte and so was also interpreting it as the modRM byte. Reported-by: likunxi@fas.harvard.edu Change-Id: I6d4bdabfa03411704c48d905c50c7b23072fc615 Reviewed-on: https://gem5-review.googlesource.com/5281 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-10-30base: Fix forcing loopback only binding for listeners.Gabe Black
Despite online documentation, the type used for sin_addr.s_addr is not actually an unsigned long, it is an in_addr_t. When an unsigned long is a 64 bit value, the endian conversion moves the relevant bits of the 32 bit in_addr_t to positions which are truncated away. This forces the value to 0 which means to bind to any interface, the opposite of the intended effect. Change-Id: I53c63dea6bd88144dfef1a9a49b478fab30a8ba2 Reviewed-on: https://gem5-review.googlesource.com/5301 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-20arch-arm: RBIT instruction using mirroring funcGiacomo Travaglini
The high speed bit-reversing function is now used for the Aarch64/32 RBIT instruction implementation. Change-Id: Id5a8a93d928d00fd33ec4061fbb586b8420a1c1b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5262 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-10-20base: Function for mirroring bits in variable length wordGiacomo Travaglini
This patch introduces a high-speed template function for mirroring the bits (MSB=>LSB) in a variable length word. The function is achieving high performances since it is using a look-up table. Change-Id: Ib0d0480e68d902f25655f74d243de305103eff75 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5261 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-10-20base: Defining make_unique for C++11Giacomo Travaglini
std::make_unique is not available for C++11 compilers, and it has been introduced only in C++14. Since gem5 is not officially supporting the latter at the moment, this patch allows to use it in gem5 if including base/compiler.hh. If compiled under C++14, std::make_unique will be used instead. Change-Id: Ibf1897fad0a1eb1cb0c683cc25170feaa6841997 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5201 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-10-19cpu-o3: Add M5_VAR_USED to variableJason Lowe-Power
Fixes compile error for gem5.fast on CLANG due to unused variable. Change-Id: Iabe777a27d75ee8bfa7b214fff577aed3c7582c7 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/4980 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-10-19scons: Fix the regression tests.Gabe Black
A recent scons cleanup introduced a small bug when setting the variant path of the regression test SConscript. When turned into a relative path, the directory can be interpreted differently depending on what it's considered relative to. When left as a scons node, there is no ambiguity. Change-Id: I162afdc4fcef81db096ec8304f81bc98fa6bf899 Reviewed-on: https://gem5-review.googlesource.com/5221 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-10-17scons: Stop generating inc.d in the isa parser.Gabe Black
Generating dependency/build product information in the isa parser breaks scons idea of how a build is supposed to work. Arm twisting it into working forced a lot of false dependencies which slowed down the build. Change-Id: Iadee8c930fd7c80136d200d69870df7672a6b3ca Reviewed-on: https://gem5-review.googlesource.com/5081 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-10-17arch-arm: Fix inverted 32/64-bit check in GDBBoris Shingarov
Change-Id: Ided438af19c9b8504d4624119c4d9fb5157c7cf0 Reviewed-on: https://gem5-review.googlesource.com/4720 Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-17util: Filter out the For-Upstream commit message tagAndreas Sandberg
Some internal review flows, e.g. the flow used by ARM Research, uses the For-Upstream tag to indicate that a change has been approved for upstream. This tag isn't meaningful outside of the internal review system. Remove it automatically when running the maintainer script to prepare patches to be posted upstream. Change-Id: Ie3745d0e8ad7a1bfddc5ec68ff3e6ff3f91ca8d8 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5141 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-10-13arch-arm: Signal an event when executing store exclusivesNikos Nikoleris
When a store exclusive is executed, whether it is successful or not, the exclusives monitor is cleared and therefore we need to signal an event for the PE. Change-Id: I383c88c769c0ac5f5d36c4b5d39c9681134d3a20 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4480 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-10-13mem: Signal the local monitor when clearing the global monitorNikos Nikoleris
ARM systems require the coordination of the global and local monitors. When the system is run without caches the global monitor is implemented in the abstract memory object. This change adds a callback from the abstract memory that notifies the local monitor when the global monitor is cleared. Additionally, for ARM systems the local monitor signals the event register and wakes the thread context up. Subsequent wait-for-event (WFE) instructions will be immediately signaled. Change-Id: If6c038f3a6bea7239ba4258f07f39c7f9a30500b Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3760 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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