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2005-08-15Changes for getting FreeBSD to run.Miguel Serrano
SConscript: Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc. arch/alpha/isa_traits.hh: Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks(). cpu/exec_context.hh: cpu/o3/alpha_cpu.hh: Replaced htoa()s with gtoh() and htog(). cpu/o3/fetch_impl.hh: cpu/simple/cpu.cc: Replaced htoa() with gtoh(). dev/disk_image.cc: Replaced htoa()s with letoh()s. dev/ide_ctrl.cc: Got rid of magic numbers. Added IdeChannel and IdeRegType type names where necessary. dev/ide_ctrl.hh: Got rid of unnecessary macros. Changed RegType_t to IdeRegType. Changed bmi_regs to allow accessing registers by name instead of just by array index. Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel. dev/ide_disk.cc: Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array. dev/ide_disk.hh: Updated command register struct. dev/ns_gige.cc: dev/ns_gige.hh: Made ReadConfig and WriteConfig begin with a lower-case letter. writeConfig() now takes a pointer to data as a parameter instead of a copy of data. dev/pciconfigall.cc: writeConfig() now takes a pointer to data as a parameter instead of a copy of data. dev/pcidev.cc: Cleaned up readConfig() and writeConfig() functions. dev/pcidev.hh: Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data. dev/pcireg.h: Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used. dev/rtcreg.h: Added macros for bit fields in RTC status registers A & B. dev/sinic.cc: Function name change: WriteConfig --> writeConfig. writeConfig() now takes a pointer to data instead of a copy of data. The accessing of elements of PCIConfig structure is updated. dev/sinic.hh: Function name change: WriteConfig --> writeConfig. writeConfig() now takes a pointer to data instead of a copy of data. dev/tsunami_io.cc: Added implementation of new RTC and PIT classes. dev/tsunami_io.hh: Added classes for RTC and PIT modules. dev/tsunamireg.h: Added macros for DMA ports used by Tsunami-Tru64. dev/uart8250.cc: Got rid of a magic number. Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register. dev/uart8250.hh: Added comments and macros dealing with the UART Interrupt ID register. kern/linux/linux_system.cc: Replaced htoa() with htog(). python/m5/objects/Pci.py: PciFake is a python class for Pci Devices that do nothing. python/m5/objects/Tsunami.py: TsunamiFake was renamed as IsaFake. sim/system.cc: Replaced htoa()s with htog()s. dev/isa_fake.cc: New BitKeeper file ``dev/isa_fake.cc'' TsunamiFake was renamed as IsaFake. dev/isa_fake.hh: New BitKeeper file ``dev/isa_fake.hh'' TsunmaiFake was renamed as IsaFake. dev/pitreg.h: New BitKeeper file ``dev/pitreg.h'' Useful macros for working with PIT (Periodic Interval Timer) registers. --HG-- extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780
2005-07-18Fix for passing functional memory param to timing mem.Steve Reinhardt
python/m5/config.py: Fix error message. --HG-- extra : convert_revision : 4e57f7bdd4ea7dfdd3e88c60080f993997b0bda2
2005-07-14Fix for bug in using compression in full-system mode.Steve Reinhardt
Involves adding functional memory param (for full-system mode only, for now). --HG-- extra : convert_revision : f42cf087969427b5406be0162e13163d3624684f
2005-07-06no license in treeNathan Binkert
--HG-- extra : convert_revision : 4a9bb7be1e7e3f465ad34b9129b7c1e0578dbfcc
2005-07-05config:Steve Reinhardt
Add license. --HG-- extra : convert_revision : af110213e79464b8f2d970a2e906d1234e818c6d
2005-06-30Initialize bpred table pointers.Steve Reinhardt
--HG-- extra : convert_revision : 9999c05b7fb8f66c2b9d5544868994f82d432d19
2005-06-30Fixes for cygwin compile.Steve Reinhardt
dev/ide_atareg.h: Need endian.h for LITTLE_ENDIAN. sim/syscall_emul.hh: Need to include sys/fcntl.h to get O_BINARY. --HG-- extra : convert_revision : 606f9506dc483f3952dcc65b8ba25c28001f2c43
2005-06-29Easier remote debugging at boot time.Nathan Binkert
sim/system.cc: Add a global variable that will tell the remote debugger to wait when a given CPU is is registered. --HG-- extra : convert_revision : a093c9331daa675d4b59a321e53a5da6ea292c40
2005-06-29Fix uninitialized variables in ide controllerNathan Binkert
dev/ide_ctrl.cc: Initialize variables to zero to avoid uninitialized usage. --HG-- extra : convert_revision : 98fd0bfc2b7530938c6ab3a55345d0e594098238
2005-06-29Allow CPUs to specify their own CPU ids.Nathan Binkert
Make the AlphaConsole calculate the number of CPUs instead of passing that in as a parameter. cpu/base.cc: pass the desired cpu_id into registerExecContext, offsetting it by the thread number. a cpu_id of -1 means that it should be generated for you. cpu/base.hh: Take the cpu_id as a parameter cpu/o3/alpha_cpu_builder.cc: cpu/simple/cpu.cc: Accept the cpu_id as a parameter while we're here, let's remove the multiplier since it is not used. dev/alpha_console.cc: don't take the number of CPUs as a parameter. Calculate it from the system based on the number of CPUs that have been registered. move init() code to startup() to ensure that all CPUs are registerd. dev/alpha_console.hh: python/m5/objects/AlphaConsole.py: don't take the number of CPUs as a parameter. move init() code to startup() to ensure that all CPUs are registerd. python/m5/objects/BaseCPU.py: take the cpu_id as a parameter. Default it to -1 which means that it will be generated. sim/system.cc: allow the registerExecContext functioin to take a desired cpu_id as a parameter. Check to ensure that the id isn't already used. Accept -1 as a request to have an id assigned. sim/system.hh: keep track of the number of registered exec contexts. provide a function for accessing the number of exec contexts that checks to ensure that they are all registered correctly. --HG-- extra : convert_revision : 8e12f96ff8a49fa16cdbbdb4c05c651376c35788
2005-06-28Don't hard code the location of m5AlphaAccess. Instead, move theNathan Binkert
code into a function that can be called by the AlphaConsole class. AlphaConsole will pass in its address. arch/alpha/ev5.hh: Move Phys2K0Seg to ev5.hh and fixup the TSUNAMI uncacheable bits so that they will be converted correctly. dev/alpha_access.h: Do not hard code the location of the AlphaConsole dev/alpha_console.cc: fixup #includes tell the system where the alpha console is sim/system.hh: Provide a function that will tell the system where the AlphaAccess structure (device) lives --HG-- extra : convert_revision : 92d70ca926151a32eebe9925de597459ac58013e
2005-06-28Pass the location of the m5 console backdoor to the consoleNathan Binkert
instead of compiling it into the console version dev/alpha_access.h: move serialization stuff to alpha_console.hh define the ALPHA_ACCESS_BASE in m5 instead of in console.c and have m5 pass the value to the console dev/alpha_console.cc: dev/alpha_console.hh: Move serialization stuff into a derived class of AlphaAccess sim/system.cc: pass the value of ALPHA_ACCESS_BASE to the console code via the m5AlphaAccess console variable. --HG-- extra : convert_revision : 0ea4ba239f03d6dad51a6efae0385aa543064117
2005-06-27Reorganize tap code so that more than one method can be usedNathan Binkert
for accessing physical packets. Add support for tap devices found on linux and bsd. --HG-- extra : convert_revision : 198b082f2e847da8471c3f22d6a55beb9f4b592e
2005-06-27Update for console code reorganizationNathan Binkert
dev/alpha_access.h: Update the ALPHA_ACCESS_VERSION move typedefs to this file since they're only used here. dev/alpha_console.cc: formatting sim/system.cc: xxm -> m5 --HG-- extra : convert_revision : 3aeca50d1385034f5a1e20dd8b0abd03bd6f26f0
2005-06-27Implement a state machine clock that acutally limits how fastNathan Binkert
the nsgige state machine can run. The frequency is of the actual state transitions, and not the rate of what underlying instructions might run at. dev/ns_gige.cc: Implement a state machine clock that acutally limits how fast the state machine can run. After each state transition, a variable is kept to hold the next state transition until the next clock. The frequency is of the actual state transitions, and not the rate of what underlying instructions might run at. dev/ns_gige.hh: Add back the rxKickEvent and txKickEvent events. python/m5/objects/Ethernet.py: Default the state machine clock to '0ns' so the default behaviour doesn't change when we actually implement the state machine clock. --HG-- extra : convert_revision : 2db1943dee4e91ea75aaee6a91e88f27f01a09dd
2005-06-27rename m5scons.py scons_helper.pyNathan Binkert
--HG-- extra : convert_revision : faaacc493b8da5d002d498e10cfa8cf004aafeed
2005-06-23Added Float classAli Saidi
Fixed printing so the tokenizer in m5 doesn't get confused Expanded NullSimObject so it could be used as an element in a VectorParam --HG-- extra : convert_revision : 661b1916967d663ab7aee891f15f7ca190deeba6
2005-06-22Move max_time and progress_interval parameters to the RootNathan Binkert
object and get rid of the ParamContext that each used to have. python/m5/objects/Root.py: Add max_time and progress_interval to the Root object sim/root.cc: Add max_time and progress_interval to the Root object. These parameters used to be in their own contexts in sim_events.cc sim/sim_events.cc: Get rid of the ParamContext for max cycles and the progress event. Move the functionality to the Root object sim/sim_events.hh: Move ProgressEvent declaration to the header so that it can be used in other files. --HG-- extra : convert_revision : ff664b806855e8eb9201b8a25392aa53204464f0
2005-06-22Merge zizzer.eecs.umich.edu:/bk/m5Nathan Binkert
into ziff.eecs.umich.edu:/z/binkertn/research/m5/head --HG-- extra : convert_revision : 9dc37bbcc1dd5669f6de4e35a7c37e54d0af5c05
2005-06-22fix tokenizeNathan Binkert
base/str.cc: Fix tokenize so that it doesn't behave incorrectly when there are empty strings. test/tokentest.cc: Clean up the test function so it's easier to see what's going on --HG-- extra : convert_revision : c7a3db7bc516d3575b1cc4ab7afbd0f1fbe1ec6f
2005-06-22Fix: opt_cpu and trace_cpu were already defined in syscall_emulationSteve Reinhardt
when I added them to the global list... SConscript: Remove opt_cpu and trace_cpu from syscall_emulation_sources to avoid double definition. --HG-- extra : convert_revision : b10a2e648249b1d742b881aa7580f8d1b0d6fbc1
2005-06-21Fix cache bug... getting a response on a writeback hitSteve Reinhardt
(from a trace replay). SConscript: Compile in trace-reader CPUs. --HG-- extra : convert_revision : 35b0da704e94b07a75fd89131028fbfbf31cf3a6
2005-06-21Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Steve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/m5 --HG-- extra : convert_revision : 32a82fce7c12b2a72bc3196a667e96d66b8b0b37
2005-06-19little bit of formattingNathan Binkert
clean up debugging a bit dev/ns_gige.cc: little bit of formatting don't break in the debugger if a packet is dropped when the receiver is disabled since it can realistically happen --HG-- extra : convert_revision : 364efa3eb16990db191085f5b847c3bb255a173c
2005-06-14Make turbolaser stuff compile againNathan Binkert
--HG-- extra : convert_revision : 61c100e4dbbf28a5282ae9d38e3e0f85e170ad54
2005-06-13Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Steve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/m5 --HG-- extra : convert_revision : 2e4050f58c1ce42187a94d3bbf79d82fe4b5f822
2005-06-13Fix assert in PhysicalMemory objectNathan Binkert
--HG-- extra : convert_revision : f1da0dde072562248ee587cb452adde3f7e1384e
2005-06-13some cleanup to turbolaser codeNathan Binkert
--HG-- extra : convert_revision : dc86cc5b7c63e4832cf8a03f6c849611d929d3b9
2005-06-13Add NFS-dbench, and iscsi dbench benchmarksNathan Binkert
--HG-- extra : convert_revision : 71e416668f4bbcf9785ea2363ec406135a217e32
2005-06-13use transactions for database accessNathan Binkert
base/mysql.hh: Add support for for transactions base/stats/mysql.cc: get rid of table locking and start using transactions base/stats/mysql_run.hh: setup()/remove()/cleanup() should be protected, not private --HG-- extra : convert_revision : ace710beb7fb689a6e25831d8032f389fc1347e7
2005-06-10Minor fixes to release scripts.Steve Reinhardt
--HG-- extra : convert_revision : 134e5281cafb2275277434132d3721bdba16c0ed
2005-06-10Add new "global" release script to util to exportSteve Reinhardt
release versions of m5, m5-test, and ext. --HG-- extra : convert_revision : b5ae04dff9defae64a90faa503015bcd2b0c8762
2005-06-09BaseSystem was renamed to SystemNathan Binkert
--HG-- extra : convert_revision : 74e03fe9447d9d2be59e675b034dc6df0afcde51
2005-06-05cache.hh:Steve Reinhardt
Add FALRU & IIC back in. --HG-- extra : convert_revision : 3c3c67abd89b61593df3ac3dffc105c10b7a7ec2
2005-06-05Statistics.py:Steve Reinhardt
get rid of python_file param --HG-- extra : convert_revision : 94816a98d4263cd2f80e52a0f891db102f1a1fde
2005-06-05changes linux process names slightlyAli Saidi
kern/linux/linux_threadinfo.hh: kern/linux/sched.hh: changed names slightly --HG-- extra : convert_revision : 8e42ebee1d749a65b78af5733de9e0deda3c548e
2005-06-05YA cache fix.Steve Reinhardt
--HG-- extra : convert_revision : a1d752e6534c826e020a972d76a4baf8aa5d5790
2005-06-05Another cache fix.Steve Reinhardt
--HG-- extra : convert_revision : 6875c6144070b9d43c480756b3863e2d987347dc
2005-06-05Fix up conditional cache stuff.Steve Reinhardt
SConscript: Get rid of prefetch & split cache files (temporarily). --HG-- extra : convert_revision : 72072c06a15ce8187adc76eb3a0b83413750e374
2005-06-05Merge zizzer.eecs.umich.edu:/bk/m5Nathan Binkert
into crampon.my.domain:/z/binkertn/research/m5/head --HG-- extra : convert_revision : 2acf413c32b571c44a6cb01b0427cf3bd31fd8e3
2005-06-05Fix documentation formatting bug.Steve Reinhardt
--HG-- extra : convert_revision : 86bb5e5b01742144869eaa2f248650468ed4f861
2005-06-05Cleanup copyright stuff. Add our copyright files thatNathan Binkert
are ours arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_tru64_process.hh: base/loader/object_file.cc: base/loader/object_file.hh: sim/process.cc: sim/process.hh: remove $Id$ string cpu/ozone/cpu.cc: cpu/ozone/cpu_impl.hh: cpu/ozone/ea_list.cc: cpu/ozone/ea_list.hh: kern/linux/sched.hh: kern/linux/thread_info.hh: Add M5 Copyright cpu/trace/opt_cpu.cc: dev/rtcreg.h: nit kern/linux/aligned.hh: kern/linux/hwrpb.hh: util/oprofile-top.py: util/stats/db.py: util/stats/dbinit.py: util/stats/display.py: util/stats/info.py: util/stats/print.py: util/stats/stats.py: Cleanup copyright --HG-- extra : convert_revision : 4274e9121ef7543e0b3999b31e935edb19c54d46
2005-06-05Add a few more files to the don't-release list.Steve Reinhardt
--HG-- extra : convert_revision : e798efa5127865398bf45fd0660b0a2e15faf14b
2005-06-05Merge zizzer:/bk/m5 into vm1.reinhardt.house:/z/stever/bk/m5Steve Reinhardt
--HG-- extra : convert_revision : 467f93b532348ed5d75e9c0b8d517a9eda59437f
2005-06-05Update for better conditional compilation of cache models.Steve Reinhardt
--HG-- extra : convert_revision : e3d7c8882ad34325fdc58cdba44165e0518ea330
2005-06-05elf_machdep.h isn't actually usedNathan Binkert
--HG-- extra : convert_revision : f67464e39462f8a8e6b9b8f5cde40a5f141909fe
2005-06-05Add simple script to clean up and exported tree for release.Steve Reinhardt
--HG-- extra : convert_revision : 73cd3fa103bd9ea22954d4748115a45410dc07a3
2005-06-05Get rid of Python stats output option.Steve Reinhardt
--HG-- extra : convert_revision : e53033a2266aed1a1d9c1c9b1c8775a3f1a3f234
2005-06-05Get rid of unnecessary doxygen config files.Steve Reinhardt
--HG-- extra : convert_revision : a87334a738a057775d1c51946928c9454a892115
2005-06-05Commit copyright-updating script.Steve Reinhardt
--HG-- extra : convert_revision : 7b8c7287395de65305552ed51ff3e3018132a78c
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