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2005-06-05Add licenses in python dir.Steve Reinhardt
python/m5/__init__.py: python/m5/convert.py: python/m5/multidict.py: python/m5/smartdict.py: Add license. --HG-- extra : convert_revision : 825dcad94e13b18aadc7188053ad1999a0219eae
2005-06-05Update for ISCA release.Kevin Lim
--HG-- extra : convert_revision : 5c3fd17ba0a5173b22d2977b278013ef50d78a68
2005-06-05Merge zizzer:/bk/m5 into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/m5Ron Dreslinski
--HG-- extra : convert_revision : 21175b3a16c1da736cf7f6fba1c327a809f5ef79
2005-06-05update for ISCA releaseRon Dreslinski
--HG-- extra : convert_revision : ab97c34b76c253267d48479bd043963be8b7fe4b
2005-06-05Merge zizzer.eecs.umich.edu:/bk/m5Nathan Binkert
into crampon.my.domain:/z/binkertn/research/m5/head --HG-- extra : convert_revision : cf1b2ab4544492aced52c0012c3a67fee188b683
2005-06-05moved uart8530 to encumbered directoryAli Saidi
--HG-- extra : convert_revision : 353e5591df9bbe5a915d226068fb2e406441d3b5
2005-06-05Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5-cleanAli Saidi
--HG-- extra : convert_revision : 0c339eb7574f59665690f7e8457eff0b21e3c4c9
2005-06-05split uart into urt8250 and uart8530Ali Saidi
fix some doxygen comments SConscript: Added split uart files dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/tsunami.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/tsunamireg.h: fix doxgyen file comment dev/uart.cc: dev/uart.hh: python/m5/objects/Uart.py: split uart into urt8250 and uart8530 --HG-- extra : convert_revision : 2e70aad892a37620d7909017648bca6d7d69d678
2005-06-05Merge zizzer:/bk/m5 into vm1.reinhardt.house:/z/stever/bk/m5Steve Reinhardt
--HG-- extra : convert_revision : 2ed9e6c9875903a2cde296155b7d1bee10fea3de
2005-06-05Import stats document from html.Steve Reinhardt
--HG-- extra : convert_revision : 0117ca5b2095b18fd079153a4f0847c9158acd9d
2005-06-05insn_fifo isn't usedNathan Binkert
--HG-- extra : convert_revision : 2a0c72a4d65a5160ce1317968e565704093291a2
2005-06-05Merge zizzer.eecs.umich.edu:/bk/m5Nathan Binkert
into crampon.my.domain:/z/binkertn/research/m5/head --HG-- extra : convert_revision : b0c9b044b44a1bfc4cded2ebfa240b799dd4a5a0
2005-06-05Minor format tweaks on config file documentation.Steve Reinhardt
--HG-- extra : convert_revision : ab88d823d6420e3cc3fc37d0b634947df384b631
2005-06-05Rewrite config file documentation for Python config.Steve Reinhardt
--HG-- extra : convert_revision : 24525d1f6e119e30943c036ffafae14c5ea25f2d
2005-06-04Fix doxgyen commentsAli Saidi
Use openbsd ide/atapi header files dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/tsunami_cchip.hh: dev/tsunami_io.hh: dev/tsunami_pchip.hh: Fix Doxygen comments dev/ide_disk.cc: Use BSD atapi/ide header files dev/ide_disk.hh: use ide/atapi header files --HG-- extra : convert_revision : a15e40c7d7cc52af6867821e9574ba5c47021721
2005-06-04Merge zizzer:/bk/m5 into zed.eecs.umich.edu:/z/hsul/work/m5/cleanLisa Hsu
--HG-- extra : convert_revision : e3646dfd2f0844e4be7f5369032f9932eb378fdb
2005-06-04get rid of bad panic.Lisa Hsu
--HG-- extra : convert_revision : e4e6ab8f163b3c93ac7c29ab8ac50f369b190dbb
2005-06-04Get rid of broken "long help" option.Steve Reinhardt
--HG-- extra : convert_revision : 8b7c646ce416d2a2a4919acbb87c0b6d65920d42
2005-06-04Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Steve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/m5 --HG-- extra : convert_revision : f12cecd1359770061b52e9f57f2aaa809e61115c
2005-06-04Clean up to work with recent python config changes.Steve Reinhardt
configs/splash2/run.py: parent is now Parent. Need to explicitly instantiate classes. --HG-- extra : convert_revision : c260fad00ca82cb1032e73af2e5caa2ad013067d
2005-06-04shuffle files around for new directory structureNathan Binkert
--HG-- rename : cpu/base_cpu.cc => cpu/base.cc rename : cpu/base_cpu.hh => cpu/base.hh rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh rename : cpu/full_cpu/smt.hh => cpu/smt.hh rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
2005-06-04Merge zizzer.eecs.umich.edu:/bk/m5Nathan Binkert
into crampon.my.domain:/z/binkertn/research/m5/head --HG-- extra : convert_revision : 7e9a7c1abf90cc1545d63caf5d6a06351ece36b5
2005-06-04Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5-cleanAli Saidi
--HG-- extra : convert_revision : cce752079ba1ae9d4043df959dc448d815e598b1
2005-06-04Fix monet configurationAli Saidi
--HG-- extra : convert_revision : fe053d8fe69cc8731161a875cbf8b78cda48e4b1
2005-06-04Remove the inorder CPUNathan Binkert
--HG-- extra : convert_revision : 626aad449df9370383becb8e14f4cbf406b5b376
2005-06-04Get rid of vestiges of .mpy file handling.Steve Reinhardt
--HG-- extra : convert_revision : 309b051be3473e2d42d3200c1af84227d01b5900
2005-06-04BaseSystem -> SystemNathan Binkert
Make System an object that can be instantiated. For operating systems that don't need any OS specific hacks. python/m5/objects/AlphaConsole.py: python/m5/objects/BaseCPU.py: python/m5/objects/Tsunami.py: BaseSystem -> System --HG-- rename : python/m5/objects/BaseSystem.py => python/m5/objects/System.py extra : convert_revision : e5d12db02abef1b0eda720b50dd2c09cb1ac5232
2005-06-04more portableNathan Binkert
arch/alpha/alpha_tru64_process.cc: Sort #includes Make code more portable. g++ doesn't seem to always like struct ::stat (and others). So, we typedef stat outside of the namespace as something else and use the typedef base/hostinfo.cc: use snprintf to quell warning base/inifile.cc: use strncpy to quell warning base/stats/events.cc: don't use strcpy cpu/beta_cpu/btb.cc: use FloorLog2 instead of log2 cpu/beta_cpu/comm.hh: cpu/beta_cpu/inst_queue.hh: cpu/beta_cpu/sat_counter.hh: use sim/host.hh instead of stdint.h --HG-- extra : convert_revision : 59bd9235dda74e72a8b6a70b3f3a981840384f3f
2005-06-03Make m5.fast workNathan Binkert
base/loader/elf_object.cc: elf_version is an odd function. Don't use assert since it has a necessary side effect. --HG-- extra : convert_revision : 8c48f91afe6c7ff5030ac1a534dcda7e2e0c5c57
2005-06-03Bug fix & cleanup in config code.Steve Reinhardt
python/m5/config.py: Bug fix: code was silently converting between incompatible SimObject types as an unintended side-effect of the object cloning support. --HG-- extra : convert_revision : 236f4fe5370f2eddf8af8fab68e2b83dccc34305
2005-06-03Additions/fixes for Tru64 syscall emulation.Steve Reinhardt
We can now run the SimpleScalar wupwise binary to completion on the test input. Didn't have time to do more testing, but I fixed a major problem w/getdirentries that should help a lot more programs run. arch/alpha/alpha_tru64_process.cc: Add truncate, ftruncate, statfs, and fstatfs. Add v4.x (pre-F64) stat, fstat, and lstat. Add setsysinfo (though all it does is provide more specific warning messages). Fix subtle but major bug in getdirentries. sim/syscall_emul.cc: sim/syscall_emul.hh: Add truncate, ftruncate, statfs, and fstatfs. --HG-- extra : convert_revision : 9037393d00dc49b0074a41603ea647587f5a9ec7
2005-06-03Make m5.fast work when there are no Trace.flagsNathan Binkert
--HG-- extra : convert_revision : 05eda14b86311013d3c32ee56f9f52ae94126fb4
2005-06-02Rename builds more descriptively:Steve Reinhardt
ALPHA -> ALPHA_SE (for Syscall Emulation) KERNEL -> ALPHA_FS KERN_TLASER -> ALPHA_FS_TL Also renamed configs/kernel dir to configs/fullsys. README: build/SConstruct: Rename builds more descriptively. --HG-- extra : convert_revision : f2bffb3ad0fc5068cc7fa20661ed9e4e7bc5b202
2005-06-02clean up command line stuffNathan Binkert
sim/main.cc: Clean uo usage output and print usage when no options are given Don't accept mpy files anymore since we don't use them. --HG-- extra : convert_revision : c3b16f602f301d2de12547285334c0037d829998
2005-06-02Fix-up some config issuesNathan Binkert
python/m5/config.py: Make NetworkBandwidth and MemoryBandwidth work python/m5/objects/Ethernet.py: Make 1Gbps default for ethernet --HG-- extra : convert_revision : 59e62f7e62624356ae8d7304598617f60667f040
2005-06-02update copyrights that are spit out on the console.Nathan Binkert
--HG-- extra : convert_revision : e927fd48d2cc82d20478baeb05f58dce07a800e7
2005-06-02More de-SimpleScalarization of cache code.Steve Reinhardt
--HG-- extra : convert_revision : b310a0e8a02487302d4861cfa08543b6047a0ff7
2005-06-02Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Steve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/m5 --HG-- extra : convert_revision : 71d4611b6d9496d3237c4d0cd46912a108ec8653
2005-06-01Change lru/iic parameter checks for licensing.Erik Hallnor
--HG-- extra : convert_revision : 5d5ae086d5e7981d49c68a2283ad2c08e27b4399
2005-06-01Get rid of unused sim/int_stats.* files.Steve Reinhardt
--HG-- extra : convert_revision : 6b86e97fbadbd6f00c0bc52f0ab07fd7741f9818
2005-06-01Rename sim/universe.{cc,hh} to root.{cc,hh} (since theSteve Reinhardt
object defined there was renamed Root long ago). SConscript: arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_tru64_process.cc: base/misc.cc: base/pollevent.cc: base/pollevent.hh: base/stats/events.cc: base/trace.hh: cpu/beta_cpu/fetch_impl.hh: cpu/beta_cpu/full_cpu.cc: cpu/beta_cpu/inst_queue_impl.hh: cpu/pc_event.cc: cpu/static_inst.cc: dev/etherbus.cc: dev/etherdump.cc: dev/etherlink.cc: dev/ide_disk.cc: dev/pcidev.cc: sim/builder.cc: sim/eventq.cc: sim/main.cc: sim/root.cc: sim/stat_control.cc: Rename sim/universe.{cc,hh} to root.{cc,hh}. --HG-- rename : sim/universe.cc => sim/root.cc extra : convert_revision : b8699e81e285253d66da75412e7bb2c251c0389a
2005-06-01Standardize clock parameter names to 'clock'.Steve Reinhardt
Fix description for Bus clock_ratio (no longer a ratio). Add Clock param type (generic Frequency or Latency). cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/beta_cpu/alpha_full_cpu_builder.cc: cpu/simple_cpu/simple_cpu.cc: dev/ide_ctrl.cc: dev/ns_gige.cc: dev/ns_gige.hh: dev/pciconfigall.cc: dev/sinic.cc: dev/tsunami_cchip.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: dev/uart.cc: python/m5/objects/BaseCPU.py: python/m5/objects/BaseCache.py: python/m5/objects/BaseSystem.py: python/m5/objects/Bus.py: python/m5/objects/Ethernet.py: python/m5/objects/Root.py: sim/universe.cc: Standardize clock parameter names to 'clock'. Fix description for Bus clock_ratio (no longer a ratio). python/m5/config.py: Minor tweaks on Frequency/Latency: - added new Clock param type to avoid ambiguities - factored out init code into getLatency() - made RootFrequency *not* a subclass of Frequency so it can't be directly assigned to a Frequency paremeter --HG-- extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
2005-06-01Get rid of obsolete simobj/SConscriptSteve Reinhardt
--HG-- extra : convert_revision : 2f2a5e1702a5ad09d80362e25a895e6181b2117c
2005-06-01A few more config updates. Works with regression now.Steve Reinhardt
configs/splash2/run.py: Update file for new config changes. python/m5/config.py: - isParamContext() not defined any more - fix bug with re-assigning vectors over scalars and vice versa --HG-- rename : configs/splash2/run.mpy => configs/splash2/run.py extra : convert_revision : 2eb28a92f8de327f6dfddd01467c61e759275f6b
2005-05-29Major cleanup of python config code.Steve Reinhardt
Special mpy importer is gone; everything is just plain Python now (funky, but straight-up). May not completely work yet... generates identical ini files for many configs/kernel settings, but I have yet to run it against regressions. This commit is for my own convenience and won't be pushed until more testing is done. python/m5/__init__.py: Get rid of mpy_importer and param_types. python/m5/config.py: Major cleanup. We now have separate classes and instances for SimObjects. Proxy handling and param conversion significantly reorganized. No explicit instantiation step anymore; we can dump an ini file straight from the original tree. Still needs more/better/truer comments. test/genini.py: Replace LoadMpyFile() with built-in execfile(). Export __main__.m5_build_env. python/m5/objects/AlphaConsole.py: python/m5/objects/AlphaFullCPU.py: python/m5/objects/AlphaTLB.py: python/m5/objects/BadDevice.py: python/m5/objects/BaseCPU.py: python/m5/objects/BaseCache.py: python/m5/objects/BaseSystem.py: python/m5/objects/Bus.py: python/m5/objects/CoherenceProtocol.py: python/m5/objects/Device.py: python/m5/objects/DiskImage.py: python/m5/objects/Ethernet.py: python/m5/objects/Ide.py: python/m5/objects/IntrControl.py: python/m5/objects/MemTest.py: python/m5/objects/Pci.py: python/m5/objects/PhysicalMemory.py: python/m5/objects/Platform.py: python/m5/objects/Process.py: python/m5/objects/Repl.py: python/m5/objects/Root.py: python/m5/objects/SimConsole.py: python/m5/objects/SimpleDisk.py: python/m5/objects/Tsunami.py: python/m5/objects/Uart.py: Fixes for eliminating mpy_importer, and modified handling of frequency/latency params. Also renamed parent to Parent. --HG-- rename : python/m5/objects/AlphaConsole.mpy => python/m5/objects/AlphaConsole.py rename : python/m5/objects/AlphaFullCPU.mpy => python/m5/objects/AlphaFullCPU.py rename : python/m5/objects/AlphaTLB.mpy => python/m5/objects/AlphaTLB.py rename : python/m5/objects/BadDevice.mpy => python/m5/objects/BadDevice.py rename : python/m5/objects/BaseCPU.mpy => python/m5/objects/BaseCPU.py rename : python/m5/objects/BaseCache.mpy => python/m5/objects/BaseCache.py rename : python/m5/objects/BaseSystem.mpy => python/m5/objects/BaseSystem.py rename : python/m5/objects/Bus.mpy => python/m5/objects/Bus.py rename : python/m5/objects/CoherenceProtocol.mpy => python/m5/objects/CoherenceProtocol.py rename : python/m5/objects/Device.mpy => python/m5/objects/Device.py rename : python/m5/objects/DiskImage.mpy => python/m5/objects/DiskImage.py rename : python/m5/objects/Ethernet.mpy => python/m5/objects/Ethernet.py rename : python/m5/objects/Ide.mpy => python/m5/objects/Ide.py rename : python/m5/objects/IntrControl.mpy => python/m5/objects/IntrControl.py rename : python/m5/objects/MemTest.mpy => python/m5/objects/MemTest.py rename : python/m5/objects/Pci.mpy => python/m5/objects/Pci.py rename : python/m5/objects/PhysicalMemory.mpy => python/m5/objects/PhysicalMemory.py rename : python/m5/objects/Platform.mpy => python/m5/objects/Platform.py rename : python/m5/objects/Process.mpy => python/m5/objects/Process.py rename : python/m5/objects/Repl.mpy => python/m5/objects/Repl.py rename : python/m5/objects/Root.mpy => python/m5/objects/Root.py rename : python/m5/objects/SimConsole.mpy => python/m5/objects/SimConsole.py rename : python/m5/objects/SimpleDisk.mpy => python/m5/objects/SimpleDisk.py rename : python/m5/objects/Tsunami.mpy => python/m5/objects/Tsunami.py rename : python/m5/objects/Uart.mpy => python/m5/objects/Uart.py extra : convert_revision : 9dc55103a6f5b40eada4ed181a71a96fae6b0b76
2005-05-28Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Steve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/m5 --HG-- extra : convert_revision : 475f25967577aa47d84b476c07ce0ddfe05078d0
2005-05-28ns_gige_reg.h, ns_gige.cc:Lisa Hsu
clean up code to eliminate license issues. dev/ns_gige.cc: dev/ns_gige_reg.h: clean up code to eliminate license issues. --HG-- extra : convert_revision : 64adbd87faa5ce5ac6b9da4fd95b12796487c8f9
2005-05-26Added copyright.Kevin Lim
--HG-- extra : convert_revision : f6d53ac5130ea9f77f39f7c1aa35eeb1d5107599
2005-05-25Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Steve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/m5 --HG-- extra : convert_revision : 13696a8e526f7ded7555d009d03bdc7551557571
2005-05-24Little debugging things.Steve Reinhardt
cpu/base_cpu.cc: Get rid of leftover debugging code. --HG-- extra : convert_revision : b33b2279499456b12a6242a9472ea5be724b37be
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 01:25:35 +0000