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2007-03-29Override addPrivateSplitL1Caches function in order to automatically set the ↵Kevin Lim
tgts_per_mshr of the caches to 20. This is needed otherwise things will potentially lock up when using the O3CPU because the caches can run out of targets, and then not respond. Remove this hack once the caches eventually get fixed. --HG-- extra : convert_revision : 8c61ac1b6182f57ebbe3bcfeddb5a4f4334d7bc0
2007-03-29Update code so that the O3 CPU can handle not initially having anything ↵Kevin Lim
hooked up to its ports. This fixes the segfault Ali recently found when using sampling. src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: Update code so that the O3 CPU can handle not initially having anything hooked up to its ports. --HG-- extra : convert_revision : 04bcef44e754735d821509ebd69b0ef9c8ef8e2c
2007-03-29Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 849b63ae1300e240082da19dfeb283cdeeb80aef
2007-03-29Fidget with the syntax of the MultiOp format in anticipation of making it ↵Gabe Black
actually work. --HG-- extra : convert_revision : f62a1f035cc11677df8eb5a839ca1247d819fab3
2007-03-29Add code to generate register and immediate based integer op microop classes.Gabe Black
--HG-- extra : convert_revision : 718f941da74dd3b4557cd21e1772879ac21aa9c6
2007-03-29Allow "let" blocks to add code to the output files.Gabe Black
--HG-- extra : convert_revision : 0ffddb2b40dccbf2a3790464c843cfc1b43eaa02
2007-03-28Call compare and Swap on the target, not the response.Ron Dreslinski
--HG-- extra : convert_revision : 522805fe2c9abaa5ba0d9262ad98f841d90f6452
2007-03-27some more fixes... non-tso stuff seems to workAli Saidi
--HG-- extra : convert_revision : da604d20443376d04826397d0aaff0bdd744053b
2007-03-27Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head --HG-- extra : convert_revision : 45b64b1564f0e4958d8441455f87b2b185324d55
2007-03-27First Pass At Cmp/Swap in cachesRon Dreslinski
--HG-- extra : convert_revision : 211bfb7c6a59e9e120dae1600d4754baaf231332
2007-03-26Instead of creating a new python process to run traceflags.py,Nathan Binkert
just directly exec the file and generate the flags --HG-- extra : convert_revision : d648ca7348404ded5337db327adafccbd2ae40c8
2007-03-26Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 4b60e96e8dc9c69842514e29925ec1931597ddb4
2007-03-26first bit of life from the intel gigabit modelAli Saidi
--HG-- extra : convert_revision : d8944a53f6b585df21651c4e624518d5c49a7837
2007-03-25Update stats for changes.Kevin Lim
--HG-- extra : convert_revision : a24c4cd7e2fcd732f5da5679f0c0fbf205f22815
2007-03-24Update for new trace data behavior.Kevin Lim
--HG-- extra : convert_revision : c3df20c5187614febc4cc9f4d4c68bfecfba1ea7
2007-03-24Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2 --HG-- extra : convert_revision : f3d193dd1e0b82c496d8224f014123b7cb028c02
2007-03-24Added a SPARC_SE simple atomic regression for the mcf benchmark.Gabe Black
--HG-- extra : convert_revision : 2284e41c03659db8fc8f284f7d9b587a3708fadf
2007-03-23Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zower.eecs.umich.edu:/home/gblack/m5/newmem-o3-spec --HG-- extra : convert_revision : 6b1c8025d29f3e8f90906805dd51a5d523d56004
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2 src/cpu/base_dyn_inst.hh: Hand merge. Line is no longer needed because it's handled in the ISA. --HG-- extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
2007-03-23Make hardware loads/stores serializing; they need to avoid certain ↵Kevin Lim
out-of-order interactions in the 21264. --HG-- extra : convert_revision : d83940af7d0e8efe891d574ac42c6d70d179e2b1
2007-03-23Updates for commit.Kevin Lim
1. Move interrupt handling to a separate function to clean up main commit() function a bit. Also gate the function call off properly based on whether or not there are outstanding interrupts, and the system is not in PAL mode. 2. Better handling of updating instruction's status bits. Instructions are not marked "atCommit" until other stages view it (pushed off to IEW/IQ), and they have been properly handled (faults). 3. Don't consider the ROB "empty" for the purpose of other stages until the ROB is empty, all stores have written back, and there was no store commits this cycle. The last is necessary in case a store committed, in which case it would look like all stores have written back but in actuality have not. src/cpu/o3/commit.hh: Slightly modify how interrupts are handled. Also include some extra bools to keep track of state properly. src/cpu/o3/commit_impl.hh: Slightly modify how interrupts are handled. Also include some extra bools to keep track of state. General correctness updates, most specifically for when commit broadcasts to other stages that the ROB is empty. --HG-- extra : convert_revision : 682ec6ccf4ee6ed0c8a030ceaba1c90a3619d102
2007-03-233 memory system fixes:Kevin Lim
1. Update packet's flags properly when a snoop happens 2. Don't allow accesses to read a block's data if the block has outstanding MSHRs. This avoids a RAW hazard in MP systems that the memory system was not detecting properly earlier (a write required a block to upgrade, and while the upgrade was outstanding, a read came along and read old data). 3. Update MSHR's request upon a response being handled. If the MSHR has more targets than it can respond to in one cycle, then its request must be properly updated to the new head of the targets list. src/mem/bus.cc: Update packet's flags properly upon snoop. src/mem/cache/cache_impl.hh: Be sure to not allow accesses to a block with outstanding MSHRs. src/mem/cache/miss/miss_queue.cc: Update MSHR's request upon a response being handled. --HG-- extra : convert_revision : 76a9abc610ca3f1904f075ad21637148a41982d6
2007-03-23Handle status bits a little better, as well as non-speculative instructions.Kevin Lim
src/cpu/o3/iew_impl.hh: Allow for slightly more flexible handling of non-speculative instructions. They can be other classes now, such as loads or stores. Also be sure to clear the state associated with squashes that are not used. i.e. if a squash due to a memory ordering violation happens on the same cycle as an older branch squashing, clear the state associated with the memory ordering violation. Lastly don't consider uncached loads to officially be "at commit" until IEW receives the signal back from commit about the load. src/cpu/o3/inst_queue_impl.hh: Don't consider non-speculative instructions to be "at commit" until the IQ has received a signal from commit about the instruction. This prevents non-speculative instructions from being issued too early. src/cpu/o3/mem_dep_unit_impl.hh: Clear instruction's ability to issue if it's replayed. --HG-- extra : convert_revision : d69dae878a30821222885485f4dee87170d56eb3
2007-03-23Two fixes:Kevin Lim
1. Requests are handled more properly now. They assume the memory system takes control of the request upon sending out an access. 2. load-load ordering is maintained. src/cpu/base_dyn_inst.hh: Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out. Also include some functions to allow certain status bits to be cleared. src/cpu/base_dyn_inst_impl.hh: Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out. src/cpu/o3/fetch_impl.hh: General correctness fixes. retryPkt is not necessarily always set, so handle it properly. Also consider the cache unblocked only when recvRetry is called. src/cpu/o3/lsq_unit.hh: Handle requests a little more correctly. Now that the requests aren't pointed to by the DynInst, be sure to delete the request if it's not being used by the memory system. Also be sure to not store-load forward from an uncacheable store. src/cpu/o3/lsq_unit_impl.hh: Check to make sure load-load ordering was maintained. Also handle requests a little more correctly. --HG-- extra : convert_revision : e86bead2886d02443cf77bf7a7a1492845e1690f
2007-03-23Set progress_interval in terms of CPU cycles.Kevin Lim
--HG-- extra : convert_revision : 76b0918276cb613eb314ab1479b5ffdb31f31dee
2007-03-23A couple of minor fixes.Kevin Lim
1. Set CPU ID in all modes for the O3 CPU. 2. Use nextCycle() function to prevent phase drift in O3 CPU. 3. Remove assertion in rename map that is no longer true. src/cpu/o3/alpha/cpu_builder.cc: Allow for CPU id in all modes, not just full system. Also include a parameter that was left out by accident. src/cpu/o3/alpha/cpu_impl.hh: Set the CPU ID properly. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: Use nextCycle() function so that the CPU does not get out of phase when starting up from quiesces. src/cpu/o3/rename_map.cc: Remove assertion that is no longer true. tests/configs/o3-timing.py: Set CPU's id to 0. --HG-- extra : convert_revision : 2b69c19adfce2adcc2d1939e89d702bd6674d5d5
2007-03-22Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : fd590d464359d8ae859998a9f446b960781a5e33
2007-03-22finish up the coding of the Intel Gb NIC... Many Many bugs to squashAli Saidi
src/dev/i8254xGBe.cc: src/dev/i8254xGBe.hh: src/dev/i8254xGBe_defs.hh: finish coding the Intel Gb NIC device src/dev/io_device.hh: we really don't want to be able to pass a null buffer to dma read, at least not the way we have things setup now... it won't work at all --HG-- extra : convert_revision : 6739497232317ec407cfa7a96de4575a9a6cfc46
2007-03-22Add structure based bitfield syntax to the isa_parser. This is primarily ↵Gabe Black
useful for x86. --HG-- extra : convert_revision : dfe6df160d00adec1830d9b88520ba20834d1209
2007-03-22Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 79c337f18d635acc176f0ca8d6e71fbc429cb258
2007-03-22Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace --HG-- extra : convert_revision : da83ee4c3251fa95faf66e8c6d3412158ffe6887
2007-03-22Fix mcf benchmark object so it gets the arguments it expects.Gabe Black
--HG-- extra : convert_revision : 47087be1f89699e9f8e0dc023abbf593bc0f6618
2007-03-21Add a junk operand. With no operands, the parser breaks.Gabe Black
--HG-- extra : convert_revision : 7410fd3681ed3d9b1293d982ed5f3553a6c75f3f
2007-03-21Start implementing groups of instructions which do the same thing on ↵Gabe Black
different sets of inputs. --HG-- extra : convert_revision : 6a5be61831588f801965dd4e80cb52f28911c320
2007-03-21put the int register count in intregs.hhGabe Black
--HG-- extra : convert_revision : c48c13d9c4606c8cb7c60d18cd0f4dac9103a501
2007-03-21Add a s SPARC_SE gzip regressionGabe Black
--HG-- extra : convert_revision : 5d75c9ad6e4599ce9b1afc176eaafab03bed43f0
2007-03-21Break out the one and two byte opcodes into different files. Also change ↵Gabe Black
what bits decode is done on to reflect where clumps of instructions are. --HG-- extra : convert_revision : 8768676eac25e6a4f0dc50ce2dc576bdcdd6e025
2007-03-21Missed a constGabe Black
--HG-- rename : src/arch/x86/isa/decoder.isa => src/arch/x86/isa/decoder/decoder.isa extra : convert_revision : a60e7495da6fe99fa2375a3f801f2962c3e41adb
2007-03-21created SPARC_SE vortex regression.Gabe Black
--HG-- extra : convert_revision : cdb60bcfbea4b79491fb035cc7ecd08cbaa2100b
2007-03-21Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace --HG-- extra : convert_revision : 41214c71e7fa11d47395975a141793337d020463
2007-03-21The m5 side of statetrace. This is fairly ugly, but I don't want to lose it.Gabe Black
--HG-- extra : convert_revision : 171b41418567c1f41f43363a46fa9aeaa58ae606
2007-03-20Ignore "time" and "times" syscalls.Gabe Black
--HG-- extra : convert_revision : 3ff55e35877c0fd74823ce5e52ed16c38da92068
2007-03-20Fixed up some types and const placement, and added signed bitfields that ↵Gabe Black
sign extend themselves. --HG-- extra : convert_revision : 84bda8fc14f9a6f7dc7982c9aeb15bf688457706
2007-03-20Added syntax for structure oriented extMachInsts.Gabe Black
--HG-- extra : convert_revision : 4a30c58019ad8e3dd8dffb4c4c08eb6914e5c5be
2007-03-19Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : a6ae6ce183aaa4d1a9434f9ddd64cc30878d2147
2007-03-19Ditched read or write only subbitfields for now since they were proving ↵Gabe Black
difficult to implement. Allow component Bitfields to be instantiated without templates, clean up the implementation a little, and adjust the comments to match. --HG-- extra : convert_revision : b9b8aea285a95eeabbb4c0233c1bce49b8c773b8
2007-03-19For the _BitfieldRO and _BitfieldWO classes, make sure the undesired ↵Gabe Black
operator is redefined as private. --HG-- extra : convert_revision : b18d8e49547c2712ab255d048850c5231313b80a
2007-03-19Formatting fixes.Gabe Black
--HG-- extra : convert_revision : 276d0667daa4626288b56af3b4b17a3f9052e81a
2007-03-19Lots and lots of comments.Gabe Black
--HG-- extra : convert_revision : 0de510464e2e002775ccd79e2922ccb0055845e5
2007-03-19Reworked the BitUnion stuff a bit. There is moderately better isolation of ↵Gabe Black
the backend parts, although there are still macros. --HG-- extra : convert_revision : e9692c5e697c96061ef70cf78ef532c99dbbd672
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