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2007-04-09Make SPARC build o3 by default.Gabe Black
--HG-- extra : convert_revision : 7be49f9d395094d849d8da59b0fd4efe962fb201
2007-04-08Take into account that the flattened integer register space is a different ↵Gabe Black
size than the architected one. Also fixed some asserts. --HG-- extra : convert_revision : 26e7863919d1b976ba8cad747af475a6f18e9440
2007-04-08Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec --HG-- extra : convert_revision : dba3542ab73cc8ae46347a14ae4c133f1276011c
2007-04-08Get the "hard" SPARC instructions working in o3. I don't like that the ↵Gabe Black
IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly. --HG-- extra : convert_revision : cfd32808592832d7b6fbdaace5ae7b17c8a246e9
2007-04-06Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 8e624bb95cb9f478ca7ac1dbbd64e20674e3e224
2007-04-06Consolidated the microcode assembler to help separate it from more ↵Gabe Black
x86-centric stuff. --HG-- extra : convert_revision : 5e7e8026e24ce44a3dac4a358e0c3e5560685958
2007-04-06Refactored the x86 isa description some more. There should be more ↵Gabe Black
seperation between x86 specific parts, and those parts which are implemented in the isa description but could eventually be moved elsewhere. --HG-- rename : src/arch/x86/isa/formats/macroop.isa => src/arch/x86/isa/macroop.isa extra : convert_revision : 5ab40eedf574fce438d9fe90e00a496dc95c8bcf
2007-04-06Clean up the code a little, fix (I think) a perceived problem with immediate ↵Gabe Black
sizes, and sign extend the 32-bit-acting-like-64-bit-immediates. --HG-- extra : convert_revision : e59b747198cc79d50045bd2dc45b2e2b97bbffcc
2007-04-06Add in a stub merging functionGabe Black
--HG-- extra : convert_revision : 15e3cdb4ebcd31bc44204687ba59dde00c56c6be
2007-04-06Clean up the macroop code.Gabe Black
--HG-- extra : convert_revision : 3cf83c3e038fece6190dbb91f56deb0498c9a70d
2007-04-06Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec --HG-- extra : convert_revision : b7e89d32df946ea24c438292308f5fc8248f8bd9
2007-04-05Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : efdbf9787383dc1df544b7276f8120285e69bf69
2007-04-04The process of going from an instruction definition to an instruction to be ↵Gabe Black
returned by the decoder has been fleshed out more. The following steps describe how an instruction implementation becomes a StaticInst. 1. Microops are created. These are StaticInsts use templates to provide a basic form of polymorphism without having to make the microassembler smarter. 2. An instruction class is created which has a "templated" microcode program as it's docstring. The template parameters are refernced with ^ following by a number. 3. An instruction in the decoder references an instruction template using it's mnemonic. The parameters to it's format end up replacing the placeholders. These parameters describe a source for an operand which could be memory, a register, or an immediate. It it's a register, the register index is used. If it's memory, eventually a load/store will be pre/postpended to the instruction template and it's destination register will be used in place of the ^. If it's an immediate, the immediate is used. Some operand types, specifically those that come from the ModRM byte, need to be decoded further into memory vs. register versions. This is accomplished by making the decode_block text for these instructions another case statement based off ModRM. 4. Once all of the template parameters have been handled, the instruction goes throw the microcode assembler which resolves labels and creates a list of python op objects. If an operand is a register, it uses a % prefix, an immediate uses $, and a label uses @. If the operand is just letters, numbers, and underscores, it can appear immediately after the prefix. If it's not, it can be encolsed in non nested {}s. 5. If there is a single "op" object (which corresponds to a single microop) the decoder is set up to return it directly. If not, a macroop wrapper is created around it. In the future, I'm considering seperating the operand type specialization from the template substitution step. A problem this introduces is that either the template arguments need to be kept around for the specialization step, or they need to be re-extracted. Re-extraction might be the way to go so that the operand formats can be coded directly into the micro assembler template without having to pass them in as parameters. I don't know if that's actually useful, though. src/arch/x86/isa/decoder/one_byte_opcodes.isa: src/arch/x86/isa/microasm.isa: src/arch/x86/isa/microops/microops.isa: src/arch/x86/isa/operands.isa: src/arch/x86/isa/microops/base.isa: Implemented polymorphic microops and changed around the microcode assembler syntax. --HG-- extra : convert_revision : e341f7b8ea9350a31e586a3d33250137e5954f43
2007-04-04Fix a regular expression problem when recognizing labels for string ↵Gabe Black
substitution. --HG-- extra : convert_revision : ba398e1b434efda28882f159d5a4419302276371
2007-04-04Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-spec --HG-- extra : convert_revision : 81269f094834f43b4e908321bfce2e031b39d2a4
2007-04-04Updates for other ISA cpu_builders.Kevin Lim
--HG-- extra : convert_revision : b02736c627bb9dcf87463a9133e04369b9f8fae2
2007-04-04Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head --HG-- extra : convert_revision : 7181d8c2ee673322372484cf288a94ebd91b5265
2007-04-04Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU ↵Kevin Lim
functions. src/cpu/o3/alpha/cpu_impl.hh: Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions. --HG-- extra : convert_revision : 74f4b1f5fb6f95a56081f367cce7ff44acb5688a
2007-04-04Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : be37463ea3ca38ef02ae0b82da0752f240a530d0
2007-04-04The MemoryObject tha owns a port should delete it if it so chooses when ↵Ali Saidi
deletePortRefs() is called on it with that port as a parameter. In this way a MemoryObject can keep a functional port around and give it to anyone who wants to do functional accesses rather than creating a new one each time. src/mem/bus.cc: src/mem/bus.hh: src/mem/cache/cache_impl.hh: only keep around one func port we give to anyone who wants it. Otherwise we can run out of port ids reasonably quickly if a lot of functional accesses are happening (e.g. remote debugging, dprintk, etc) --HG-- extra : convert_revision : 6a9e3e96f51cedaab6de1b36cf317203899a3716
2007-04-04Reworking how x86's isa description works. I'm adopting the following ↵Gabe Black
definitions to make figuring out what's what a little easier: MicroOp: A single operation actually implemented in hardware. MacroOp: A collection of microops which are executed as a unit. Instruction: An architected instruction which can be implemented with a macroop or a microop. --HG-- extra : convert_revision : 1cfc8409cc686c75220767839f55a30551aa6f13
2007-04-04Make "Name" really be the same as "name" with only the first letter ↵Gabe Black
capitalized. Before, it had the first letter capitalized but all the others lower case --HG-- extra : convert_revision : bcbb28f2bf268765c1d37075a4417a4a6c1b9588
2007-04-04Made x86 ExtMachInsts distinguishable from each other by defining a real == ↵Gabe Black
and a real hash function. --HG-- extra : convert_revision : 30f29a36f6ab44e67e62aaf81b685fbe1267c746
2007-04-04Added all the different variations of the register names.Gabe Black
--HG-- extra : convert_revision : ff06bdca556a5e1a0dfe7978575c2277c30c002a
2007-04-04Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head --HG-- extra : convert_revision : 4a8cbb65b19636c31b5c6fd5f24c90f8f2148ed1
2007-04-03Made the "data" field of store queue entries into a character array. It's ↵Gabe Black
sized to match an IntReg which was what it used to be, but we might want to make it something architecture independent. All data is now endian converted before entering the store queue entries which simplifies store to load forwarding in "trans endian" simulations, and makes twin memory ops work. src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: fixed twin memory operations. --HG-- extra : convert_revision : 8fb97f98e285cd22413e06e146fa82392ac2a590
2007-04-03Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemAli Saidi
into zizzer.eecs.umich.edu:/tmp/newmem.1449b --HG-- extra : convert_revision : 05021f4884de7af769df9f9c4416c483baa9c2fe
2007-04-03fixed sttw instruction changes execution trace a bitAli Saidi
--HG-- extra : convert_revision : 4bebe6f9acedfd29dfe02f16d4ddb551a2fc7290
2007-04-03Fix a memory leak. Hopefully this fixes the longer running benchmarks.Kevin Lim
--HG-- extra : convert_revision : 89eff82642ff181a9b95c77c4d2bf620ca837113
2007-04-03Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 7be8ebe55a7b11552d78701520f93aa86db1e501
2007-04-03A batch of changes and fixes. Macroops are now generated automatically, ↵Gabe Black
multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented. --HG-- extra : convert_revision : 518059f47e11df50aa450d4a322ef2ac069c99c9
2007-04-03Zero out ModRM if the byte isn't there, and fix some displacement size stuff.Gabe Black
--HG-- extra : convert_revision : f43abf33a223a665b30098c63011fb162200d5e6
2007-04-02Remove/comment out DPRINTFs that were causing a segfault.Kevin Lim
The removed ones were unnecessary. The commented out ones could be useful in the future, should this problem get fixed. See flyspray task #243. src/cpu/o3/commit_impl.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rob_impl.hh: Remove/comment out DPRINTFs that were causing a segfault. --HG-- extra : convert_revision : b5aeda1c6300dfde5e0a3e9b8c4c5f6fa00b9862
2007-04-02Fix up SPARC's CPU builder to match changes to Alpha's CPU builder.Kevin Lim
--HG-- extra : convert_revision : ec2a739f1da07f0922c772e6998017995115ce80
2007-03-30Update refs for recent changes.Kevin Lim
--HG-- extra : convert_revision : 30a02eec4d83c4e1708ed0a4e2b5faea88fe8e03
2007-03-29Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 2f7f50f4ad31f741c0c67db96e49d30ca078fc94
2007-03-29make serialization at least seem to workAli Saidi
--HG-- extra : convert_revision : cbfdb64f9a204670b8dd0294c74a17044b9f330c
2007-03-29Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : e6a6c65cb0f8df9af82daa3eebd989c4211edfb0
2007-03-29Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemGabe Black
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-mcf --HG-- extra : convert_revision : f2c3503e8893b957330cf3791748a45800ea5a82
2007-03-29Added SPARC_SE simple timing twolf regression.Gabe Black
--HG-- extra : convert_revision : 289aadd4bc762a5a9e7a82ee15196ebdea2521e5
2007-03-29Added a SPARC_SE simple timing mcf regression.Gabe Black
--HG-- extra : convert_revision : d8fea11c37bd3f0b5f5e8880c92b711892ee8125
2007-03-29get rid of CWP bounds warning...Ali Saidi
--HG-- extra : convert_revision : 74df09341c091c2d6ca9b46c6a3521f22b48acf4
2007-03-29add to instruction test sttw instructionAli Saidi
--HG-- extra : convert_revision : 16efbe12e609a909a589505ad6c473eb44c38f9c
2007-03-29Made the MultiOp format do a little more. It now sets up single microop ↵Gabe Black
instructions to return an instance of the right class. The code to decode register numbers and generate loads and stores still needs to be added. Also, a syntax for specifying operands as sources, destinations, or both needs to be established. Multipl microop instructions are also not handled, pending real macroop generation support. --HG-- extra : convert_revision : 1a0a4b36afce8255e23e3cdd7a85c1392dda5f72
2007-03-29Add a microcode assembler. A microcode "program" is a series of statements. ↵Gabe Black
Each statement has an optional label at the beginning, a capitilized microcode class name which is roughly equivalent to a mnemonic in a regular ISA, and then an optional series of operands seperated by white space. The operands are either a decimal constant, a label, or a code fragment surrounded by non nested {}s. Labels are a letter or underscore followed by letters, underscores, or digits. The syntax for describing code segments might need to be changed if a need arrises to have {}s in the code itself. --HG-- extra : convert_revision : 8e5cfdd1a3c9a7e3731fdf6acd615ee82ac2b9b7
2007-03-29Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemGabe Black
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-vortex --HG-- extra : convert_revision : 709766f1a1a2347c92d4f508e38b9602c1030717
2007-03-29Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemGabe Black
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-vortex --HG-- extra : convert_revision : 7efa5fe80ef75155685b93453e967a1115318b9d
2007-03-29Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemGabe Black
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-gzip --HG-- extra : convert_revision : 39cf24fe19cd48306baef1ef147a3f4738d0fe8a
2007-03-29Added SPARC_SE simple timing vortex regression.Gabe Black
--HG-- extra : convert_revision : 12a2fc0b43cfa72747c1ef24d124979e43b166c7
2007-03-29Added SPARC_SE simple timing gzip regression.Gabe Black
--HG-- extra : convert_revision : 3d5f5f991c9b0c1c07499a2013119240cae5870f
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