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2018-07-28arch-riscv: Add support for trap value registerAlec Roelke
RISC-V has a set of CSRs that contain information about a trap that was taken into each privilegel level, such as illegal instruction bytes or faulting address. This patch adds that register, modifies existing faults to make use of it, and adds a new fault for future use with handling page faults and bad addresses. Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 Reviewed-on: https://gem5-review.googlesource.com/11135 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2018-07-28arch-riscv: Add support for fault handlingAlec Roelke
This patch adds support for handling RISC-V faults, including tracking current and previous execution privilege, correctly switching to the privilege mode specified by CSRs, and setting/storing the PC. It also includes changes introduced by patch #9821, which disables interrupts during handling of a fault. Change-Id: Ie9c0f29719620c20783540d3bdb2db44f6114fc9 Reviewed-on: https://gem5-review.googlesource.com/9161 Maintainer: Alec Roelke <ar4jc@virginia.edu> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-07-27misc: Update CONTRIBUTING with gerrit changesJason Lowe-Power
Change-Id: I39b5a784a056195a5e71fd21b3abb5fc91ab70e7 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/11872
2018-07-26base: Fix ucontext compilation error for macOSGiacomo Travaglini
ucontext functions (like getcontext, setcontext etc) have been marked as deprecated and are hence hidden in latest macOS releases. This patch uncovers them; warnings wil be produced but compilation won't fail since -Wno-error=deprecated-declarations flag is currently used. Change-Id: Ic10e6f77a38875828b1891eaed2f0626ecffff67 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11729 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-25cpu: Warn when (un)serializing a traffic generatorGiacomo Travaglini
When checkpointing a system with a traffic generator, a warning is produced so that the user is reminded serialization does not keep all the traffic generator internal state. Change-Id: I3c49c912c9ff3a4208f55b2da0a88fc694147280 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11831 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-25cpu: Allow creation of traffic gen from generic SimObjectsGiacomo Travaglini
This patch allows to instantiate a Traffic generator starting from a generic SimObject, so that linking to a BaseTrafficGen only is no longer mandatory. This permits SimObjects different than a BaseTrafficGen to instantiate generators and to manually specify the MasterID they will be using when generating memory requests. Change-Id: Ic286cfa49fd9c9707e6f12a4ea19993dd3006b2b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11789 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-07-25mem-cache: TempCacheBlk allocates and destroys its own dataRobert Kovacsics
This change is because I want to make CacheBlk::data private, so that I can track all the places which write to it. But to keep that commit smaller (it is pretty big, because of all the places which might change it), I have split this into a commit of its own. Change-Id: I15a2fc1752085ff3681f5c74ec90be3828a559ea Reviewed-on: https://gem5-review.googlesource.com/11829 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-07-24systemc: Flesh out the sc_port implementation slightly.Gabe Black
This makes other files compile because it changes the relationship between constructors,etc., slightly. Change-Id: I8d9a6e12ec640a82da166fe05c4f5e91f3f608de Reviewed-on: https://gem5-review.googlesource.com/10840 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-24systemc: Stub out the predefined channels.Gabe Black
Change-Id: Ie030aad26875bd49e54981ec1e9076b7b5af6630 Reviewed-on: https://gem5-review.googlesource.com/10839 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-24systemc: Add systemc and systemc.h header files.Gabe Black
These are the header files as defined by the standard, although some predefined channel types and most of the sc_dt namespace have yet to be stubbed out, and so those portions are excluded. Change-Id: Ic70f887c06e591974a4265c820eb0fdfa740d19a Reviewed-on: https://gem5-review.googlesource.com/10838 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-24systemc: Stub out the sc_spawn related classes and functions.Gabe Black
Change-Id: I79f695cca97aaae9af324eb18cab073f42f0a193 Reviewed-on: https://gem5-review.googlesource.com/10837 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-24systemc: Stub out the sc_process_handle class.Gabe Black
Change-Id: I2250ccb369e0a5f2b9172d35662a9ce5e41ab1c1 Reviewed-on: https://gem5-review.googlesource.com/10836 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-24systemc: Seperate the "external" header interface.Gabe Black
Most (but not all) of the SystemC headers are part of the "external" interface that an existing, standard compliant module would include through <systemc.h> or <systemc>. Since those follow slightly different rules (relative includes, no gem5 includes), this change separates them out so that they're easier to identify. Also, this change moves the other files into a "core" subdirectory, with the intention to add a "dt", aka data type, directory some time in the future when those standard defined types are implemented. Change-Id: Ida63f9cc0bc0431024d4dd691cc5b22b944a99a8 Reviewed-on: https://gem5-review.googlesource.com/10835 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-24systemc: Stub out the sc_module class and related functions.Gabe Black
Change-Id: I2c20717fe1f750bf7ae84de79726b1503ec6e1cd Reviewed-on: https://gem5-review.googlesource.com/10834 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-24systemc: Add a stubbed out implementation of the sc_sensitive class.Gabe Black
This sc_sensitive class is mostly implementation defined, but has a few standards defined methods. Change-Id: I7157f6bfaaef38b5804b19a1de9f3f0aff08b697 Reviewed-on: https://gem5-review.googlesource.com/10833 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-24systemc: Add a stub implementation for sc_attr related classes.Gabe Black
Change-Id: I59ba11f71b5412643ea7026df91587fafa0c6fda Reviewed-on: https://gem5-review.googlesource.com/10832 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-24cpu-o3: Missing freeing the heads of DepGraph in IQ squashingHanhwi Jang
Free the squahsed instructions' heads of DepGraph in IQ squashing In a system with large register file (ex.2048), the number of DynInst hits the hardcoded limit (1500). This is caused by missing freeing the heads of DepGraph in IQ. IQ only clears out the heads when instructions reach writeback stage. If a instruction is squashed before writeback stage, its head of dependency graph, which holds the instruction's DynInstPtr, would not be cleared out. This prevents freeing the DynInst of the squahsed instruction even after it is committed. Change-Id: I05b3db93cb6ad8960183d7ae765149c7f292e5b3 Reviewed-on: https://gem5-review.googlesource.com/7481 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-23systemc: Add a stubbed out sc_event_finder class.Gabe Black
The standard defines this class very loosely, and so there isn't much in the stub definition. Change-Id: I2f8d07927a4eb087235e345a09d5a4d4891413b5 Reviewed-on: https://gem5-review.googlesource.com/10831 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-23systemc: Implement a stub version of the sc_prim class.Gabe Black
Change-Id: Iad32f6e385e62dc10491783c1e5cdd5d9bfcc3e6 Reviewed-on: https://gem5-review.googlesource.com/10830 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-23systemc: Add stubbed out versions of sc_port and sc_export.Gabe Black
Change-Id: I04edb5da995212f9179eeb7a97486031eea71aff Reviewed-on: https://gem5-review.googlesource.com/10829 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-23systemc: Add stubbed out versions of sc_event and related classes.Gabe Black
Change-Id: Id45c80cbb8774d8469d4df6ce7915161df977de0 Reviewed-on: https://gem5-review.googlesource.com/10828 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-23systemc: Add stubbed out versions of the sc_time functions.Gabe Black
Change-Id: Ie7e3eac0382dc2ed861eaa9ea53ab11069812db8 Reviewed-on: https://gem5-review.googlesource.com/10827 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-23systemc: Add the sc_nbdefs.hh header from Accellera.Gabe Black
This header defines the uint64 type alias needed for the sc_time class. Change-Id: I7793dbfb98001796c8c8fe24f69fe7868249ff85 Reviewed-on: https://gem5-review.googlesource.com/10826 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-23systemc: Add a stub version of the sc_interface class.Gabe Black
Change-Id: Iad1da472e13b0e16ad4de03f456ca0a001e69b51 Reviewed-on: https://gem5-review.googlesource.com/10825 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-23systemc: Hook up sc_main.Gabe Black
sc_main is exported as a python method on the SystemC_Kernel class and takes a series of string arguments. The internal c++ implementation converts those arguments into the standard argc and argv and uses them to call the standard SystemC version of that function. A weak SystemC version of sc_main is provided so that systemc will compile with or without a simulation provided version of that function. The weak version just complains and dies. Change-Id: Iad735536c37c8bc85d06cf24779f607ae4309b8b Reviewed-on: https://gem5-review.googlesource.com/10824 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-23systemc: Partially implement the sc_module_name class.Gabe Black
This class is mostly implemented as defined by the spec, except that it doesn't maintain the module name stack (which doesn't yet exist). Change-Id: I05fdc4aa40fb0497b0165824baee87ebf01a7821 Reviewed-on: https://gem5-review.googlesource.com/10823 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-23mem: Rename Packet::checkFunctional to trySatisfyFunctionalRobert Kovacsics
Packet::checkFunctional also wrote data to/from the packet depending on if it was read/write, respectively, which the 'check' in the name would suggest otherwise. This renames it to doFunctional, which is more suggestive. It also renames any function called checkFunctional which calls Packet::checkFunctional. These are - Bridge::BridgeMasterPort::checkFunctional - calls Packet::checkFunctional - MSHR::checkFunctional - calls Packet::checkFunctional - MSHR::TargetList::checkFunctional - calls Packet::checkFunctional - Queue<>::checkFunctional (of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h) - Instantiated with Queue<WriteQueueEntry> and Queue<MSHR> - WriteQueueEntry - calls Packet::checkFunctional - WriteQueueEntry::TargetList - calls Packet::checkFunctional - MemDelay::checkFunctional - calls QueuedSlavePort/QueuedMasterPort::checkFunctional - Packet::checkFunctional - PacketQueue::checkFunctional - calls Packet::checkFunctional - QueuedSlavePort::checkFunctional - calls PacketQueue::doFunctional - QueuedMasterPort::checkFunctional - calls PacketQueue::doFunctional - SerialLink::SerialLinkMasterPort::checkFunctional - calls Packet::doFunctional Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5 Reviewed-on: https://gem5-review.googlesource.com/11810 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-20mem: Removed "using namespace std;" from src/mem/packet.ccRobert Kovacsics
To avoid unintentional variable capture, all std calls must be prefixed. These are the identifiers which are in the std namespace (according to https://en.cppreference.com/w/cpp/symbol_index), but that will remain unprefixed with this change: int8_t int16_t int32_t int64_t uint8_t uint16_t uint32_t uint64_t The (u)int types are included from the packet header file, which includes <inttypes.h>, where they occur in the global namespace. They are in the std namespace in <cinttypes>/<cstdint>. There is an occurrence of "set" in this file, which is "Packet::set" and not "std::set", so it is not prefixed with the std namespace Change-Id: I7f6c0b61b09658e224fe31a9f73150b81861d6f8 Reviewed-on: https://gem5-review.googlesource.com/11809 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-19mem: Fix off-by-one error in checkFunctional, and simplify itRobert Kovacsics
There was an off-by-one error in the isRead() case, as `val_end` and `func_end` pointed to the last byte to write to (not one past the last byte), and thus `*_end - *_start` was not the length of the data to memcpy. This was correct in the case of val_start >= func_start && val_end <= func_end where `overlap_size = size`, but if it were (as the other cases suggest) `overlap_size = val_end - val_start`, then it would also be off by one. Also, the isWrite() case catered for this. I simplified the four ifs into one case which uses min/max (this is how I spotted the inconsistency). Change-Id: Ib5c5da084652e752f6baf1eec56b51b4f0f5c95c Reviewed-on: https://gem5-review.googlesource.com/11750 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-07-19mem-cache: Typo in comment: 'proceed' -> 'precede'Robert Kovacsics
The writebacks happen before anything below, not after. Change-Id: I7eaefbbf33aa17c496255dedd964a56118a28741 Reviewed-on: https://gem5-review.googlesource.com/11749 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-17dev, arm: accept and ignore writes to GIC APRn registersCiro Santilli
Otherwise the Linux kernel v4.17 boot fails with error: Tried to write Gic cpu at offset 0xd0 Change-Id: Ie8063212c9e2b29e2e4766801b4b9538e9eccbf8 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11590 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-07-16systemc: Add a stub kernel SimObject.Gabe Black
The guts of this class will be added in later changes. Change-Id: I3582c40f88f7d9ba6028a6f0a8ee5c32924a65bf Reviewed-on: https://gem5-review.googlesource.com/10822 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-07-16systemc: Add a stubbed out sc_object class.Gabe Black
Also add a SConsopt variable USE_SYSTEMC to hide systemc support until it's usable. Change-Id: Ibb37483432b147ee690a36bb5c8dd74f1c4c7ae4 Reviewed-on: https://gem5-review.googlesource.com/10821 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-07-16arch-arm: Introduce ARMv8.1 Virtual Timer System RegistersGiacomo Travaglini
Adding CNTHV_CTL_EL2, CNTHV_CVAL_EL2, CNTHV_TVAL_EL2 System Registers into the decode tree. They are currently implemented as a generic timer and produces a warning if accessed. Change-Id: I1a23035d67f95eeac49d890283e9a0d58426d504 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11592 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-07-16arch-arm: Introduce RAS System RegistersGiacomo Travaglini
Adding RAS Extension System Registers into the decode tree. They are currently unimplemented and produce a warning (not failure) if accessed. Change-Id: I4baeded822c9582a2cb9d5277409b029eb00a962 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11591 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-07-13configs: Update the DRAM sweep script to use PyTrafficGenAndreas Sandberg
Instead of generating a text configuration, use the new Python-based traffic generator. Change-Id: I6fb88ec45b74bb87470aa265af18b5a2ff24c314 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11519 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-07-13cpu: Add a Python-enabled traffic generatorAndreas Sandberg
The current traffic generator relies on a configuration file that describes a small machine to generate stimuli. This configuration file is usually generated by the gem5 Python configuration. This creates an unnecessary and fragile step. This changeset introduces a Python-based trace module. When instantiated, the module exposes a start method that takes an iterable object as a parameter (e.g., a generator). The iterable object is expected to represent a list of generators that will be run one after the other. For example: system.tgen = PyTrafficGen() m5.instantiate() def trace(): yield system.tgen.createIdle(1000) yield system.tgen.createExit(0) system.tgen.start(trace()) Change-Id: I58e60ca517e86c197859f4daaa67750066abdc1c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11518 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-07-13cpu: Support trace termination in BaseTrafficGenAndreas Sandberg
Make the BaseTrafficGen handle cases where getNextPacket() can't find a new packet and returns NULL. In that case, assume the generator has run out of packets and switch to the next generator. Change-Id: I5ca6ead550005812fb849ed9ce6b5007a65ddfa7 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11517 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-07-13cpu: Unify error handling for address generatorsAndreas Sandberg
Unify error handling and create factory methods for address generators. Change-Id: Ic3ab705e1bb58affd498a7db176536ebc721b904 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11516 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-07-13cpu: Split the traffic generator into two classesAndreas Sandberg
The traffic generator currently assumes that it is always driven from a configuration file. Split it into a base class (BaseTrafficGen) that handles basic packet generation and a derived class that implements the config handling (TrafficGen). Change-Id: I9407f04c40ad7e40a263c8d1ef29d37ff8e6f1b4 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11515
2018-07-10misc: Fix BaseCPU doxygenJason Lowe-Power
Doxygen was stopping with #include "arch/null/cpu_dummy.hh" so the html for BaseCPU was only the three functions defined in the dummy CPU. This forces doxygen to skip this #include correctly. Note: The file references for base_cpu still aren't quite right, but it's better than it was. Change-Id: Ifafe247df2511caee2569d534bd29348a5ce9e8e Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/11649 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2018-07-09arch-riscv: enable rudimentary fs simulationRobert
These changes enable a simple binary to be simulated in full system mode. Additionally, a new fault was implemented. It is executed once the CPU is initialized. This fault clears all interrupts and sets the pc to a reset vector. Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88 Reviewed-on: https://gem5-review.googlesource.com/9061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-09arch-riscv: Fix the srlw and srliw instructions.Austin Harris
Change-Id: I14ccb0655819887db2306fee1188e1c83a991743 Signed-off-by: Austin Harris <austinharris@utexas.edu> Reviewed-on: https://gem5-review.googlesource.com/11669 Reviewed-by: Alec Roelke <alec.roelke@gmail.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2018-06-29base: Add a M5_PUBLIC and M5_LOCAL attribute macroAndreas Sandberg
There are cases where we need to limit the symbol visibility to avoid compilation errors. This is a problem for Python code that relies on PyBind11 since recent versions enforce hidden symbols. As a consequence, classes that have member variables from PyBind11 need to be declared with the hidden attribute (or gem5 needs to be compiled with -fvisibility=hidden). Change-Id: I30e582fde494ff61ab7a596a595efc26a2952a5f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11513 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-06-28python: Fix call bug in @cxxMethod when override is TrueAndreas Sandberg
Change-Id: Ifa9efbd329fd01eb13100bc6690e651df2c12294 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Javier Setoain <javier.setoain@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11514 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-28cpu: Remove reduntant protobuf includesAndreas Sandberg
Change-Id: Ic34b94b3a2ea951bc023cfce2d09ce304a602e41 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11512 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-06-28python: Fixup incorrect syntax in PyBind argument handlerAndreas Sandberg
Change-Id: Ie81104d89b554795ec1020d5ce4edcf28795eda8 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11511 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-28mem: Add a memory delay simulatorAndreas Sandberg
Add a memory system component that delays traffic. The base functionality to delay packets is implemented in the abstract MemDelay class. This class exposes three methods that control packet delays: * delayReq(pkt) * delayResp(pkt) * delaySnoopResp(pkt) These methods should be specialized to implement delays for specific packet types. The class SimpleMemDelay uses the MemDelay base class to implement constant delays for read/write requests and responses. The intention is that these classes can be used for rapid prototyping of components that add a small fixed delay and the same throughput as the interconnect. I.e., any buffering done in the base class will be small and proportional to the introduced delay. Change-Id: I158cb85f20e32bfdbcbfed66a785b4b2dd47b628 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nicholas Lindsey <nicholas.lindsay@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11521 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-28arch-arm: Fix incorrect t{0,1}sz field in TTBCRAndreas Sandberg
The t0sz and t1sz fields in TTBCR only are only three bits wide unlike aarch64 which has a 6-bit wide field. The higher bits of the aarch64-equivalent should be treated as RES0. Change-Id: I60df73105c34500c0348a44a491c117e9b28f18f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11589 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-28base: Add an asymmetrical Coroutine classGiacomo Travaglini
This patch is providing gem5 a Coroutine class to be used for instantiating asymmetrical coroutines. Coroutines are built on top of gem5 fibers, which makes them ucontext based. Change-Id: I7bb673a954d4a456997afd45b696933534f3e239 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11195 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
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