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AgeCommit message (Expand)Author
2015-04-22syscall_emul: update x86 syscall tableMonir Mozumder
2015-04-22syscall_emul: update getrlimit to use warnBrandon Potter
2015-04-22syscall_emul: fix warning with wrong syscall nameBrandon Potter
2015-04-22base: add new ChunkGenerator method to identify last chunkBrandon Potter
2015-04-20stats: update a few stats from long O3 runsSteve Reinhardt
2015-04-20cpu: Remove the InOrderCPU from the treeAndreas Hansson
2015-04-20config: Remove memory aliases and rely on class nameAndreas Hansson
2015-04-15Added tag stable_2015_04_15 for changeset e17949745150Nilay Vaish
2015-04-14stats: x86: changes due to recent patchesNilay Vaish
2015-04-14config, cpu: fix progress interval for switched CPUsMalek Musleh
2015-04-13cpu: re-organizes the branch predictor structure.Dibakar Gope
2015-04-13x86: implements x87 mult/div instructionsNilay Vaish
2015-04-13ruby: allow restoring from checkpoint when using DRAMCtrlLena Olson
2015-04-13sim: Use NULL instead of None for testing filenames.Nilay Vaish
2015-04-13sim: fix function for emulating dup()Nilay Vaish
2015-04-08config: Support full-system with SST's memory systemCurtis Dunham
2015-04-08ext: Add SST connectorCurtis Dunham
2015-04-03stats: updates due to recent changesets.Nilay Vaish
2015-04-03dev: (un)serialize fix for the RTC and RTC Timer Interrupt eventsNikos Nikoleris
2015-04-03sim: correct check for endianessRuslan Bukin
2015-04-03dev: Extend access width for IDE control registersRuslan Bukin
2015-04-03cpu: fix system total instructions accountingNikos Nikoleris
2015-04-03x86: fix debug trace output for mwaitLena Olson
2015-03-27arm, configs: Do not forward snoops from I cacheAndreas Hansson
2015-03-27mem: Support any number of master-IDs in stride prefetcherStephan Diestelhorst
2015-03-27mem: Allocate cache writebacks before new MSHRsAndreas Hansson
2015-03-27mem: Cleanup flow for uncacheable accessesAndreas Hansson
2015-03-27mem: Ignore uncacheable MSHRs when finding matchesAndreas Hansson
2015-03-27mem: Remove redundant allocateUncachedReadBuffer in cacheAndreas Hansson
2015-03-27mem: Modernise MSHR iterators to C++11Andreas Hansson
2015-03-27tests: Update stats for cache block alignmentAndreas Hansson
2015-03-27mem: Align all MSHR entries to block boundariesAndreas Hansson
2015-03-27mem: Rename PREFETCH_SNOOP_SQUASH flag to BLOCK_CACHEDAli Jafri
2015-03-26sim: Update limit_event reuse to final versionCurtis Dunham
2015-03-26cpu: Fix InstPBTrace inheritanceAndreas Hansson
2015-03-23mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMWSteve Reinhardt
2015-03-23config: expand '~' and '~user' in pathsSteve Reinhardt
2015-03-23misc: quote args in echoed command lineSteve Reinhardt
2015-03-23config: Add ability to exit simulation after initializationCurtis Dunham
2015-03-23sim: Reuse the same limit_event in simulate()Curtis Dunham
2015-03-23mem: Tidy up RequestAndreas Hansson
2015-03-23tests: Final reclassification of quick regressionsAndreas Hansson
2015-03-19stats: update Minor stats due to PF bug fixSteve Reinhardt
2015-03-19tests: Recategorise regressions based on run timeAndreas Hansson
2015-03-19test, arm: Add scripts to test checkpointsAndreas Sandberg
2015-03-19config: Add soak test for memtest.pyAndreas Hansson
2015-03-19arm: Add a GICv2m deviceMatt Evans
2015-03-19arm: Remove the 'magic MSI register' in the GIC (PL390)Matt Evans
2015-03-19config: Specify OS type and release on command lineChris Emmons
2015-03-19cpu: Fix TrafficGen message formatWendy Elsasser
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