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2010-08-17tests: update reference config.ini files for previous csetSteve Reinhardt
Rename 'responder_set' to 'use_default_range'.
2010-08-17bus: clean up default responder code.Steve Reinhardt
Clean up some minor things left over from the default responder change in rev 9af6fb59752f. Mostly renaming the 'responder_set' param to 'use_default_range' to actually reflect what it does... old name wasn't that descriptive in the first place, but now it really doesn't make sense at all. Also got rid of the bogus obsolete assignment to 'bus.responder' which used to be a parameter but now is interpreted as an implicit child assignment, and which was giving me problems in the config restructuring to come. (A good argument for not allowing implicit child assignments, IMO, but that's water under the bridge, I'm afraid.) Also moved the Bus constructor to the .cc file since that's where it should have been all along.
2010-08-14Inorder: Fix compilation of m5.fast.Gabe Black
printMemData is only used in DPRINTFs. If those are removed by compiling m5.fast, that function is unused, gcc generates a warning, that gets turned into an error, and the build fails. This change surrounds the function definition with #if TRACING_ON so it only gets compiled in if the DPRINTFs do to.
2010-08-13Merge with head.Gabe Black
2010-08-13CPU: Add readBytes and writeBytes functions to the exec contexts.Gabe Black
2010-08-13InOrder: Clean up some DPRINTFs that print data sent to/from the cache.Gabe Black
2010-08-13CPU: Tidy up endianness handling for mmapped "IPR"s.Gabe Black
2010-08-12util/m5/m5.c: ensure readfile() buffer pages are in page tableJoel Hestness
(and marked dirty, in case that matters) by touching them beforehand
2010-08-12TimingSimpleCPU: fix NO_ACCESS memory op handlingJoel Hestness
When a request is NO_ACCESS (x86 CDA microinstruction), the memory op doesn't go to the cache, so TimingSimpleCPU::completeDataAccess needs to handle the case where the current status of the CPU is Running and not DcacheWaitResponse or DTBWaitResponse
2010-08-08None, not noneNathan Binkert
2010-07-27.hgignore: added src/doxygenSteve Reinhardt
2010-07-27ARM: Add regression testsAli Saidi
2010-07-22Power: The condition register should be set or cleared upon a system callTimothy M. Jones
return to indicate success or failure.
2010-07-22LSQ Unit: After deleting part of a split request, set it to NULL so that itTimothy M. Jones
isn't accidentally deleted again later (causing a segmentation fault).
2010-07-22Port: Only indicate that a SimpleTimingPort is drained if its send event isTimothy M. Jones
not scheduled, as well as the transmit list being empty.
2010-07-22O3CPU: Fix a bug where stores in the cpu where never marked as split.Timothy M. Jones
2010-07-22Syscall: Don't close the simulator's standard file descriptors.Timothy M. Jones
2010-07-22O3CPU: O3's tick event gets squashed when it is switched out. When repeatedlyTimothy M. Jones
switching between O3 and another CPU, O3's tick event might still be scheduled in the event queue (as squashed). Therefore, check for a squashed tick event as well as a non-scheduled event when taking over from another CPU and deal with it accordingly.
2010-07-22Power: Provide a utility function to copy registers from one thread contextTimothy M. Jones
to another in the Power ISA.
2010-07-21stats: unify the two stats distribution type betterNathan Binkert
2010-07-21stats: cleanup a few small problems in statsNathan Binkert
2010-07-21python: add a sorted dictionary classNathan Binkert
It would be nice if python had a tree class that would do this for real, but since we don't, we'll just keep a sorted list of keys and update it on demand.
2010-07-21python: Add mechanism to override code compiled into the exectuableNathan Binkert
If the user sets the environment variable M5_OVERRIDE_PY_SOURCE to True, then imports that would normally find python code compiled into the executable will instead first check in the absolute location where the code was found during the build of the executable. This only works for files in the src (or extras) directories, not automatically generated files. This is a developer feature!
2010-07-21Fix x86 XCHG macro-op to use locked micro-ops for all memory accessesTushar Krishna
2010-07-17SimObject: transparently forward Python attribute refs to C++.Steve Reinhardt
This tidbit was pulled from a larger patch for Tim's sake, so the comment reflects functions that haven't been exported yet. I hope to commit them soon so it didn't seem worth cleaning up.
2010-07-15ARM: Make an SRS instruction with a bad mode cause an undefined instruction ↵Gabe Black
fault.
2010-07-13ARM: Adjust the FP_Base_DepTag to be larger than the largest int reg index.Gabe Black
2010-07-08cache: fix bug in SC upgrade handlingSteve Reinhardt
This bug was introduced with the recent rework of SC failure handling in cset f97b62be544f.
2010-07-08garnet: Added topology print function to Garnet printStatsBrad Beckmann
2010-07-08NetworkMessage copy constructor fixTushar Krishna
2010-07-05checkpointing: another small overload fixSteve Reinhardt
On Nate's advice, overload 'char' as well as 'signed char' and 'unsigned char'.
2010-07-05sim: allow SimObject subclasses to define classmethodsSteve Reinhardt
(without requiring a leading underscore) Also a little cleanup on type names in SimObject.py.
2010-07-05sim: fold StartupCallback into SimObjectSteve Reinhardt
There used to be a reason to have StartupCallback be a separate object, but not any more. Now it's just confusing.
2010-07-05checkpointing: minor cleanup.Steve Reinhardt
Move some static checkpoint stuff into the Checkpoint object namespace.
2010-07-05checkpointing: fix minor bugSteve Reinhardt
Somehow we now need to explicitly specialize on 'signed char' and not just 'char' to catch cases like int8_t
2010-07-05util: add a script for testing checkpointingSteve Reinhardt
See comments in util/checkpoint-tester.py for details.
2010-07-05process: get rid of some unused code & varsSteve Reinhardt
2010-07-05process: minor format/style cleanupSteve Reinhardt
2010-06-22style: updated garnet to match M5 coding styleTushar Krishna
2010-06-28inorder: remove another debug statKorey Sewell
2010-06-26inorder: remove debugging statKorey Sewell
m5 doesnt do stats specific to binary and this resource request stat is probably only useful for people who really know the ins/outs of the model anyway
2010-06-25inorder: update regressions from RAS fixKorey Sewell
2010-06-25inorder: Return Address Stack bugKorey Sewell
the nextPC was getting sent to the branch predictor not the current PC, so the RAS was returning the wrong PC and mispredicting everything.
2010-06-25inorder: resource scheduling backendKorey Sewell
replace priority queue with vector of lists(1 list per stage) and place inside a class so that we have more control of when an instruction uses a particular schedule entry ... also, this is the 1st step toward making the InOrderCPU fully parameterizable. See the wiki for details on this process
2010-06-25X86: Fix div2 flag calculation.Gabe Black
2010-06-24inorder: update regressionsKorey Sewell
2010-06-24inorder: cleanup virtual functionsKorey Sewell
remove the annotation 'virtual' from function declaration that isnt being derived from
2010-06-24inorder: enforce 78-character ruleKorey Sewell
2010-06-24inorder: exe_unit_stats for resolved branchesKorey Sewell
2010-06-23inorder: squash from memory stallKorey Sewell
this applies to multithreading models which would like to squash a thread on memory stall