| Age | Commit message (Expand) | Author |
|---|
| 2017-07-17 | x86: Add stats to X86 TLB | Swapnil Haria |
| 2017-07-17 | riscv: Define register index constants using literals | Alec Roelke |
| 2017-07-14 | riscv: Disambiguate between the C and C++ versions of isnan and isinf. | Gabe Black |
| 2017-07-14 | tests: Upate RISC-V binaries and results | Alec Roelke |
| 2017-07-14 | riscv: Fix bugs with RISC-V decoder and detailed CPUs | Alec Roelke |
| 2017-07-14 | riscv: Add unused attribute to some registers.hh constants | Alec Roelke |
| 2017-07-13 | arch-arm: fix ldm of pc interswitching branch | Gedare Bloom |
| 2017-07-12 | ruby: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | arm: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | dev: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | net: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | testers: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | kvm, mem: Refactor some Event subclasses into lambdas | Sean Wilson |
| 2017-07-12 | cpu: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | gpu-compute: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-12 | sim, gdb: Refactor some Event subclasses into lambdas | Sean Wilson |
| 2017-07-12 | mips, x86: Refactor some Event subclasses into lambdas | Sean Wilson |
| 2017-07-12 | util,arch-arm: Added python script to generate ARM FS binaries | Pau Cabre |
| 2017-07-12 | cpu, sim: Add param to force CPUs to wait for GDB | Jose Marinho |
| 2017-07-11 | arch-riscv,tests: Add insttests for RV64C | Alec Roelke |
| 2017-07-11 | arch-riscv: Add support for compressed extension RV64C | Alec Roelke |
| 2017-07-11 | arch-riscv: Restructure ISA description | Alec Roelke |
| 2017-07-10 | dev-arm: Add ID registers to the GIC model | Jose Marinho |
| 2017-07-10 | arch-arm: Support PMU evens in the 0x4000-0x4040 range | Jose Marinho |
| 2017-07-10 | dev-arm: Don't unconditionally overwrite bootloader params | Jose Marinho |
| 2017-07-10 | dev: Fix OnIdle test in DmaReadFifo | Rohit Kurup |
| 2017-07-10 | dev: Fix address type promotion issues in VirtIO devices | Sascha Bischoff |
| 2017-07-10 | sim: Fix clashing stat names in TickedObject and Ticked | Jose Marinho |
| 2017-07-07 | kvm, arm: don't create interrupt events while saving GIC state | Curtis Dunham |
| 2017-07-07 | kvm, arm: Don't forward IRQ/FIQ when using the kernel's GIC | Andreas Sandberg |
| 2017-07-05 | arch: ISA parser additions of vector registers | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | arch: added generic vector register | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Result refactoring | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Simplify the rename interface and use RegId | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Physical register structural + flat indexing | Nathanael Premillieu |
| 2017-07-05 | arch, cpu: Architectural Register structural indexing | Nathanael Premillieu |
| 2017-07-05 | arm,kvm: update CP15 timer model when exiting Kvm | Curtis Dunham |
| 2017-07-05 | dev,arm: add Kvm mode of operation for CP15 timer | Curtis Dunham |
| 2017-07-05 | dev,arm: remove and recreate timer events around drains | Curtis Dunham |
| 2017-07-05 | kvm: move Kvm check from ARM Kvm GIC to System | Curtis Dunham |
| 2017-07-04 | config, arm: Don't import timing models for missing CPUs | Andreas Sandberg |
| 2017-07-03 | config: Clean up core timing model discovery | Andreas Sandberg |
| 2017-07-03 | config: Move core timing models to config/common/cores | Andreas Sandberg |
| 2017-07-03 | config: Make ex5_*.py independent of old configs | Andreas Sandberg |
| 2017-06-30 | config: Add missing import of 'fatal' in CpuConfig | Andreas Sandberg |
| 2017-06-30 | config: Make some MemConfig options optional | Andreas Sandberg |
| 2017-06-29 | arm: Fix memleak in Pl390 by adding destructor | Sean Wilson |
| 2017-06-29 | arm: Fix memleak in VGic by adding destructor | Sean Wilson |
| 2017-06-27 | mem-cache: Add missing overrides to BaseCache | Andreas Sandberg |
