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2006-03-28Merge m5.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem --HG-- extra : convert_revision : 762df7bf15e8e22a8fab8bbcd933047d1c8cdfa9
2006-03-28Moving towards compilation.Gabe Black
arch/sparc/isa/decoder.isa: Fixed comments so they don't comment out the ending braces of the format specifier. --HG-- extra : convert_revision : 3f037c0a17abd0dff71d22fdcd95959c3670e88a
2006-03-26Add the bus and connector objects to sconsAli Saidi
change getPort parameter from char* to string Add an extra phase between construction and init called connect SConscript: Add the bus and connector objects to scons cpu/simple/cpu.cc: cpu/simple/cpu.hh: the connection to memory shouldn't be made until we know the memory object exists (e.g. after construction) dev/io_device.hh: change to const string mem/bus.hh: change getPort parameter from char* to string initialize num_interfaces mem/mem_object.hh: change getPort parameter from char* to string mem/physical.cc: mem/physical.hh: change getPort parameter from char* to string get rid of the bus object I created last time python/m5/objects/PhysicalMemory.py: get rid of the bus object I created last time sim/main.cc: sim/sim_object.cc: sim/sim_object.hh: Add an extra phase between construction and init called connect --HG-- extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9
2006-03-25update for objects having a busAli Saidi
--HG-- extra : convert_revision : 96b5494b7d0b5ca702ac69cfa0bf8c4d44e1cc3b
2006-03-25Implement a very very simple busAli Saidi
requestTime -> time responseTime -> packet.time Make CPU and memory able to connect to the bus dev/io_device.cc: update for request and packet both having a time hand platform off to port for eventual selection of request modes dev/io_device.hh: update for request and packet both havig a time hand platform off to port for eventual selection of request modes mem/bus.hh: Add a device map struct that maps a range to a portId - Which needs work it theory it should be an interval tree - but it is a list and works fine right now Add a function called findPort which returns port for an addr range Add a deviceBlockSize function that really shouldn't exist, but it was easier than fixing the translating port mem/packet.hh: add a time to each packet mem/physical.cc: mem/physical.hh: python/m5/objects/PhysicalMemory.py: Make physical memory take a MemObject parameter of what to connect to mem/request.hh: remove requestTime/responseTime for just time in request which is requset time and the time in the packet which is responsetime python/m5/objects/BaseCPU.py: Instead of memory cpu connects to any memory object python/m5/objects/Bus.py: Fix for new bus object --HG-- extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d
2006-03-21Merge zizzer:/bk/newmemAli Saidi
into zeep.eecs.umich.edu:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : 45dba22ecbdfc8e1bb0df1efd06a37f40d56b67f
2006-03-21Make PioPort/DmaPort,DmaDevice/PioDevice compile.Ali Saidi
Add another type to the PacketResult enum of Unknown Seperate time into requsetTime and responseTime. dev/io_device.cc: dev/io_device.hh: Make PioPort/DmaPort,DmaDevice/PioDevice compile. mem/packet.hh: Add another type to the PacketResult enum of Unknown (e.g. no state set yet) mem/request.hh: Seperate time into requsetTime and responseTime. --HG-- extra : convert_revision : c6394cb838013296caea6492275252b8cae2882f
2006-03-19Merge zizzer:/bk/newmemKorey Sewell
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips --HG-- extra : convert_revision : db8490e41ec17fc8f4e2dc9548ecdc7d28b4cdd1
2006-03-19support for unaligned memory accessKorey Sewell
arch/mips/isa/base.isa: disassembly fixes arch/mips/isa/decoder.isa: support for unaligned loads/stores arch/mips/isa_traits.hh: edit Syscall Reg values arch/mips/linux_process.cc: call writevFunc on writev syscall --HG-- extra : convert_revision : 4aea6d069bd7ba0e83b23d2d85c50d68532f0454
2006-03-18Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5Steve Reinhardt
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head sim/process.cc: Fix bad auto merge (m5 changes unnecessary in newmem). --HG-- extra : convert_revision : a3ced4cd1668cd47bd02430872ca68b1433aae98
2006-03-18more syscall fixesKorey Sewell
arch/mips/isa_traits.hh: use syscall return function from alpha arch/mips/linux_process.cc: fix some syntax errors, map some functions to the desc. table --HG-- extra : convert_revision : 75e8e8893b7d96bb4fc8e8eced53bd16c0a727d1
2006-03-18Merge zizzer:/bk/newmemKorey Sewell
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips --HG-- extra : convert_revision : 1646b4fb065e3ed9d8de22e3f5c3aa05a2ef01b6
2006-03-18steps toward making syscalls workKorey Sewell
arch/mips/isa/decoder.isa: arch/mips/isa_traits.hh: sim/syscall_emul.cc: make syscall instruction functional arch/mips/linux_process.cc: add all MIPS/Linux syscalls to descriptor list --HG-- extra : convert_revision : 5455a345e76be921e9f63b248aef874b6358e465
2006-03-17Fixed a couple typosGabe Black
--HG-- extra : convert_revision : 2ffbfc4755e46a119c9709d6a5e9ddc41fde45e0
2006-03-17Merge m5.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem arch/sparc/isa/decoder.isa: Hand merged --HG-- extra : convert_revision : 5d5338602c48be48978972a091c5e93f9dd775aa
2006-03-17An attempt to get byteswap to work accross more machines.Gabe Black
--HG-- extra : convert_revision : 4a73507206cf287a89e1d496b2a08cfd1fafdf4d
2006-03-17Clean up and fix for compilationGabe Black
--HG-- extra : convert_revision : c4e66cd678313f7fe169787cb1bf3e45f114c4fd
2006-03-16clean up condition codes a little bitAli Saidi
put back in Tcc code that was deleted in last merge arch/sparc/isa/bitfields.isa: clean up condition codes a little bit --HG-- extra : convert_revision : c554fd5c3ee8cfd6643f69f8351124a7a4b5d9fa
2006-03-16fix to LiveProcess (this change got deleted somehow)Korey Sewell
--HG-- extra : convert_revision : fe4b7dc5b7d583e1d890648ba98bb0daf722a704
2006-03-16Merge zizzer:/bk/newmemKorey Sewell
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips --HG-- extra : convert_revision : 02fe0b0170348dc6f6a985c15123806088a8c23e
2006-03-16Found and fixed 3 decoder.isa bugs!!! Now the hello_world program runs for a ↵Korey Sewell
while before getting in a infinite loop. It actually "tries" to syscall too, but syscalls aren't implemented just yet arch/mips/faults.cc: more descriptive names for faults (will help future users as well as me!) arch/mips/isa/base.isa: make sure we are printing out "BasicOp" format disassembly instructions as dest,src,src instead of src,src,dest arch/mips/isa/decoder.isa: FIX LW/SW Bug!!!! I was actually loading a byte instead of a word FIX JALR Bug!!!! I was not saving the link address in R31 for this instruction FIX SLL/NOP Bug!!! We now recognize the varying flavors of sll,nop,ehb,& ssnop correctly base/loader/elf_object.cc: change back to original way base/loader/elf_object.hh: change back to original! --HG-- extra : convert_revision : 39b65fba31c1842ac6966346fe8a35816a4231fa
2006-03-16Merge m5.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem arch/sparc/isa/decoder.isa: SCCS merged --HG-- extra : convert_revision : 460843b49bc96b3fbc5897828c23f9cf9b010ae0
2006-03-16Fixups towards compiling.Gabe Black
arch/alpha/types.hh: Moved the DependenceTags enum from types to constants. arch/sparc/faults.cc: arch/sparc/faults.hh: Corrected a misspelling of PriviledgeOpcode and PrivilegedAction. arch/sparc/isa/formats.isa: Fixups towards compiling. Added a few additional instruction formats. --HG-- extra : convert_revision : 4c5506877b71b8a5c8c45db41192cf759cdac374
2006-03-16Don't forget to check in the needed header file for the conditional prefetch ↵Ron Dreslinski
building. --HG-- extra : convert_revision : 2c2562da323fa1249af72af3a89c7666c745ae2b
2006-03-16Add warning for ignored loadable ELF segments.Steve Reinhardt
base/loader/elf_object.cc: Print warning if there are more than two loadable segments. We currently assume there are at most two (text & data), and that's held so far, but it would be nice not to silently ignore others. --HG-- extra : convert_revision : 1b3e693e95ba1210b09528b97819a7fa86426edc
2006-03-15Merge zizzer:/bk/newmemKorey Sewell
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips --HG-- extra : convert_revision : 9bdde9b5bd3049744451eda1134f080b7c4b1b59
2006-03-15implement the Tcc instruction to call syscall.Ali Saidi
arch/sparc/isa/bitfields.isa: the trap field is 7:0 arch/sparc/isa/decoder.isa: add code to in the Tcc instruction to call a syscall arch/sparc/isa_traits.hh: We need the syscall num register --HG-- extra : convert_revision : 0861ec1dd8c7cac57765b22bc408fdffbe63fe2a
2006-03-15Merge zizzer:/z/m5/Bitkeeper/m5Ron Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/m5 --HG-- extra : convert_revision : a4de274ec50821218121ba38f9215f2348262c27
2006-03-15Add support for conditional compiling in of prefetchers.Ron Dreslinski
--HG-- extra : convert_revision : 357554632f102224357c8c3848bc4bc7cbb9dc54
2006-03-15add translations for new sections that are mmapped or when the brkAli Saidi
is changed Add a default machine width parameter Arch based live processes arch/alpha/linux/process.cc: arch/alpha/linux/process.hh: arch/alpha/process.cc: arch/alpha/process.hh: arch/alpha/tru64/process.cc: arch/alpha/tru64/process.hh: arch/mips/linux_process.cc: arch/mips/process.cc: arch/mips/process.hh: arch/sparc/linux/process.cc: arch/sparc/linux/process.hh: arch/sparc/process.cc: arch/sparc/process.hh: configs/test/test.py: python/m5/objects/Process.py: sim/process.cc: sim/process.hh: Architecture based live processes arch/mips/isa_traits.hh: arch/sparc/isa_traits.hh: Add a default machine width parameter mem/port.hh: gcc 4 really wants a virtual destructor sim/byteswap.hh: remove the comment around long and unsigned long even though uint32_t and int32_t are defined. Seems to work with gcc 4 and 3.4.3. sim/syscall_emul.cc: sim/syscall_emul.hh: add translations for new sections that are mmapped or when the brk is changed --HG-- extra : convert_revision : e2f9f228113c7127c87ef2358209a399c30ed5c6
2006-03-15add mips simple test in config directoryKorey Sewell
configs/test/hello_mips: hello world mips binary --HG-- extra : convert_revision : 5a495e1bfb1cbddc0879f8e80c02bd7435a02acb
2006-03-15infinitesimal small baby steps toward MIPS actually workingKorey Sewell
arch/mips/isa/formats/branch.isa: let user know that we alter r31 in disassembly arch/mips/isa_traits.cc: add copyRegs function ... comment out serialize float code for now arch/mips/isa_traits.hh: make FloatRegFile a class ... change values of architectural regs arch/mips/process.cc: change MIPS to Mips base/loader/elf_object.cc: get global pointer initialized to a value base/loader/elf_object.hh: Add global_ptr to elf_object constructor base/loader/object_file.hh: MIPS to Mips base/traceflags.py: SimpleCPU trace flag cpu/simple/cpu.cc: DPRINTF flags for SimpleCPU cpu/static_inst.hh: Add Decoder functions to static_inst.hh --HG-- extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459
2006-03-15Don't access init_regs directly. This does not affect newmem; Steve already ↵Kevin Lim
changed this in newmem. --HG-- extra : convert_revision : 19b1ed0bb2c8bcde72843e62f73635e84adf95b5
2006-03-14Merge zizzer:/bk/newmemKorey Sewell
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem --HG-- extra : convert_revision : 054833d2f7019b9a1247efc4451ccb143242059d
2006-03-14Minor Sconscript edit ... mips decoder changes ... initialize NNPC and ↵Korey Sewell
output fault name in simple cpu SConscript: Separate Alpha EIO from syscall building for other architectures arch/isa_specific.hh: change MIPS constant to 34k arch/mips/isa/decoder.isa: Allow sll,ssnop,nop, and ehb to be determined through decoder using the different types of default cases arch/mips/isa/formats/branch.isa: Delete debug code arch/mips/isa/formats/noop.isa: add a Nop format arch/mips/isa_traits.hh: use constants instead of enums arch/mips/process.cc: point to the correct header file cpu/simple/cpu.cc: Output the actual fault name sim/process.cc: Inititalize NNPC --HG-- extra : convert_revision : adb0026dfad25b14c98fb03c98bfe9c681bba6f8
2006-03-14Remove unneeded header files.Ron Dreslinski
Add some forward declerations. Fix ordering problem of variables in constructor (see sourceforge) Factor out code from header into _impl file to speed building process (keep cache_builder smaller in size) --HG-- extra : convert_revision : 20087f88f95628af716094e09c2287e09580149e
2006-03-14added *.swpGabe Black
--HG-- extra : convert_revision : 90e4387da5bbe5e3f05c4d25713d6a362c6724e8
2006-03-14Fixed up after a hand merge.Gabe Black
arch/alpha/utility.hh: Got rid of unnecessary extern and static qualifiers, and fixed up the hand merge. arch/sparc/regfile.hh: Fixed up SPARC after a hand merge. --HG-- extra : convert_revision : 56e2d90ddd144f3386dbea50fa96cfc461d46b81
2006-03-14Merge m5.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem cpu/cpu_exec_context.cc: Hand merge --HG-- rename : arch/alpha/registerfile.hh => arch/alpha/regfile.hh extra : convert_revision : bd18966f7c37c67c2bc7ca2633b58f70ce64409c
2006-03-14Moved registerfile.hh to regfile.hhGabe Black
--HG-- rename : arch/alpha/registerfile.hh => arch/alpha/regfile.hh extra : convert_revision : 27df93cd2259dab85057f966c801c0db2cb6f022
2006-03-14Added the sparc regfile.hh to bitkeeperGabe Black
--HG-- extra : convert_revision : 7bc8ca989a4f0225ad5644980c8dbc34b0c0e35f
2006-03-14SPARC clean up towards compilability.Gabe Black
--HG-- extra : convert_revision : 156670995fa61599e763b002cd70f31f19b108d1
2006-03-14Missed this in the float register changeset.Gabe Black
--HG-- extra : convert_revision : 35e967fb39fc16e38da13ab1a093d7d0916cffeb
2006-03-14Moved some full system functions into utility.hhGabe Black
--HG-- extra : convert_revision : dd2cd11213890b30975fdabdf7d9bc4652511434
2006-03-14Changed the floating point register file into a class with appropriate ↵Gabe Black
accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt. arch/alpha/arguments.cc: Renamed readFloatRegInt to readFloatRegBits arch/alpha/ev5.cc: Removed the Double from setFloatRegDouble arch/alpha/registerfile.hh: Changed the floating point register file from a union of arrays to a class with appropriate accessor functions. The interface is necessary for SPARC. arch/alpha/types.hh: Changed the FloatReg type from a union of uint64_t and double to a double, and defined a new type FloatRegBits which is a uint64_t and is used to return the bits which compose a floating point register rather than the value of the register. arch/isa_parser.py: Adjusted the makeRead and makeWrite functions to generate the new versions of readFloatReg and setFloatReg. base/remote_gdb.cc: kern/tru64/tru64.hh: Replaced setFloatRegInt with setFloatRegBits cpu/cpu_exec_context.cc: Removed the duplicated code for setting the floating point registers, and renamed the function to setFloatRegBits and readFloatRegBits. cpu/cpu_exec_context.hh: cpu/exec_context.hh: cpu/o3/alpha_cpu_impl.hh: cpu/o3/alpha_dyn_inst.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/regfile.hh: cpu/ozone/cpu.hh: cpu/simple/cpu.hh: Implemented the new versions of the floating point read and set functions. cpu/simple/cpu.cc: Replaced setFloatRegDouble with setFloatReg --HG-- extra : convert_revision : 3dad06224723137f6033c335fb8f6395636767f2
2006-03-13Have a copyRegs function defined in the ISA that copies registers from one ↵Kevin Lim
ExecContext to another ExecContext. This makes it easier for anything that needs to copy architected registers to do so in an ISA independent fashion. arch/alpha/ev5.cc: copyIprs now copies from a source ExecContext to a destination ExecContext. arch/alpha/registerfile.hh: Have ISA specific functions to copy all architected registers from one ExecContext to another. cpu/cpu_exec_context.cc: Call the ISA in order to copy any architected registers. --HG-- extra : convert_revision : 056cc3b3a9f345535d5a57c6524b114bbd5ae3c8
2006-03-12Add simple eio-based test.Steve Reinhardt
--HG-- extra : convert_revision : 969e8fddad1b87eaa294857945a4c46cb175984d
2006-03-12Oops, this goes with the previous changeset!Steve Reinhardt
mem/mem_object.hh: Change getPort() to be anonymous by default. --HG-- extra : convert_revision : 6998885ddccfbf26bc470112f40c3f19913ba7e2
2006-03-12Replace Memory with MemObject; no need for two different levels of hierarchy ↵Steve Reinhardt
there. Get rid of addPort(). Change getPort() behavior on PhysicalMemory. SConscript: cpu/simple/cpu.hh: sim/system.cc: sim/system.hh: Replace Memory with MemObject. cpu/base.hh: No need to declare Port here anymore. cpu/cpu_exec_context.hh: Need PageTable definition. cpu/simple/cpu.cc: mem/physical.cc: mem/physical.hh: Replace Memory with MemObject. Get rid of addPort(); allow getting anonymous ports with getPort(). mem/translating_port.hh: Remove unneeded header. sim/process.cc: Replace Memory with MemObject. Change how initialization port gets set up to deal with change in addPort()/getPort(). Current solution is not ideal but it works. sim/process.hh: Remove unneeded headers and declarations. Make LiveProcess::getDesc() abstract instead of panicing if called. sim/syscall_emul.hh: Fix includes. --HG-- extra : convert_revision : 11d4ffb54230038afcf7219cc46e51f809329a2f
2006-03-12Get rid of "Functional" suffix from (read|write)(Blob|String) functions.Steve Reinhardt
--HG-- extra : convert_revision : 1456308af0fd686dff53ec1baddd7747354e1c0a
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 11:48:04 +0000