Age | Commit message (Collapse) | Author |
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various ids as LiveProcess parameters.
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/process.hh:
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/process.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/solaris/process.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters.
src/kern/tru64/tru64.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters. Also fit tru64 in with the new way to handle stat calls.
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extra : convert_revision : 0198b838e5c09a730065dc6f018738145bc96269
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into ewok.(none):/home/gblack/m5/newmem
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into zeep.pool:/z/saidi/work/m5.newmem.head
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configs/common/Benchmarks.py:
add annotate test app
src/SConscript:
add annotate.cc to lis
src/arch/alpha/isa/decoder.isa:
add annotate instructions
src/base/traceflags.py:
Add annotate trace flag
src/sim/pseudo_inst.cc:
src/sim/pseudo_inst.hh:
add annotate pseudo ops
util/m5/m5op.S:
util/m5/m5op.h:
add anotate ops
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Includes support for printing readable VectorPort and Proxy names
(via __str__).
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committed.
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Significant revamp of Port code.
Some cleanup of SimObject code too, particularly to
make the SimObject and MetaSimObject implementations of
__setattr__ more consistent.
Unproxy code split out of print_ini().
src/python/m5/multidict.py:
Make get() return None by default, to match semantics
of built-in dictionary objects.
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and resulting recursive import trickiness.
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extra : convert_revision : 1ea93861eb8d260c9f3920dda0b8106db3e03705
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Some tweaking to deal with mutually recursive imports.
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rename : src/python/m5/config.py => src/python/m5/SimObject.py
extra : convert_revision : 166f7bfabfd20100e93d26a89382469465859988
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Import of changes for auto-generation of C++ param structs
from my old m5 working directory.
This code is *broken* because pieces need to be shuffled around
to satisfy name dependencies, but that really messes up the
diff, so I want to make an intermediate commit here.
src/python/m5/config.py:
Import of changes for auto-generation of C++ param structs
from my old m5 working directory.
This code is *broken* because pieces need to be shuffled around
to satisfy name dependencies, but that really messes up the
diff, so I want to make an intermediate commit here.
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the live process
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Clean up help output.
util/regress:
Clean up help output.
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extra : convert_revision : 8375d58a9d72e1871a15690991dc8fc60d47a2b3
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into vm1.(none):/home/stever/bk/newmem-head
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extra : convert_revision : 8b0fbb6b1ea38d01d048381f18fd95ab63c4c0f1
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to make it more usable by regular folks.
util/regress:
Get rid of extra stuff only needed by cron job,
to make it more usable by regular folks.
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extra : convert_revision : e113c05af5eec846db526d734cce8ff66aa95d72
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build_opts/ALPHA_SE:
Add O3CPU to default CPU model list.
tests/SConscript:
Add o3-timing configuration.
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extra : convert_revision : 378feacc07cefdaf1e2df9080c9b9d5d71e4d2a1
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Don't consider it a success if no stats at all were found.
tests/diff-out:
Don't consider it a success if no stats at all were found.
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extra : convert_revision : 733f10abdf17d1f7eeca912f84f3df37e56fe510
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
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throughout CPU models
src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA
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allowing derived classes to be simplified.
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configs/example/se.py:
Add missing cpu mem param.
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implementing faligndata more correctly.
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Verify that BAR sizes are powers of two.
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