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AgeCommit message (Expand)Author
2008-02-26X86: Get PCI config space to work, and adjust address space prefix numbering ...Gabe Black
2008-02-26Update make release, README, and RELEASE_NOTES for b5Ali Saidi
2008-02-26Bus: Update the stats for the recent bus fix.Gabe Black
2008-02-26Bus: Fix the bus timing to be more realistic.Gabe Black
2008-02-22add instruction count fast forwaing and max instruction optionsVilas Sridharan
2008-02-19Added ARM_SE as a build option.Stephen Hines
2008-02-16Update stats for new writeback behavior.Steve Reinhardt
2008-02-16Make L2+ caches allocate new block for writeback missesSteve Reinhardt
2008-02-16Update stats for some unknown minor x86 changesSteve Reinhardt
2008-02-14CPU: move the PC Events code to a place where the code won't be executed mult...Ali Saidi
2008-02-14Configs: Change Simulation.py to return a subclass of the CPU models rather t...Ali Saidi
2008-02-11Update copyright datesAli Saidi
2008-02-11Automated merge with file:/home/stever/hg/m5-origSteve Reinhardt
2008-02-11EXTRAS now points to src instead of needing 'src' subdir.Steve Reinhardt
2008-02-11Wait to set BUILD_DIR until *after* env is copied.Steve Reinhardt
2008-02-10Bus: Only update port cache when there is an item to update it with.Nicolas Zea
2008-02-10IGbE: Fix a couple of bugs.Ali Saidi
2008-02-10Fix #include lines for renamed cache files.Steve Reinhardt
2008-02-10Rename cache files for brevity and consistency with rest of tree.Steve Reinhardt
2008-02-06Make the Event::description() a const functionStephen Hines
2008-02-05Add base ARM code to M5Stephen Hines
2008-02-05Cleaned up os.path imports a bit.Steve Reinhardt
2008-02-05Make EXTRAS work for SConsopts too.Steve Reinhardt
2008-01-23X86: Put an SMBios/DMI table in memory.Gabe Black
2008-01-23X86: Optomize the bit scanning instruction microassembly a little. More can b...Gabe Black
2008-01-22X86: Implement and attach the BSR and BSF instructions.Gabe Black
2008-01-21X86: Fill out group17 in the decoder.Gabe Black
2008-01-21X86: Use the existing boot_osflags instead of duplicating it.Gabe Black
2008-01-16Update long o3 regressions for o3 change in previous changesetAli Saidi
2008-01-15Update O3 ref outputs: very minor stats change due to previous cset.Steve Reinhardt
2008-01-14The reason is that the event is supposed to put the instructions ready to exe...Ke Meng
2008-01-12X86: Redo the bit test instructions.Gabe Black
2008-01-12X86: Fix the wrmsr instruction.Gabe Black
2008-01-12X86: Make the effective segment base shadow the regular one, not the selector.Gabe Black
2008-01-12X86: Make the IO ports work using extra physical address lines. Add a serial ...Gabe Black
2008-01-12X86: Fix the general IO instructions dataSize.Gabe Black
2008-01-06Temporary fix for ll/sc bug see flyspray task for more info:Geoffrey Blake
2008-01-02Very minor memtest regression stats changes from recent coherence bug fixes.Steve Reinhardt
2008-01-02Add ReadRespWithInvalidate to handle multi-level coherence situationSteve Reinhardt
2008-01-02Mark cache-to-cache MSHRs as downstreamPending when necessary.Steve Reinhardt
2008-01-02Don't DPRINTF in the middle of a PrintReq.Steve Reinhardt
2008-01-02Bug fix: functional cache port now needs otherPort set.Steve Reinhardt
2008-01-02Additional comments and helper functions for PrintReq.Steve Reinhardt
2008-01-02Add functional PrintReq command for memory-system debugging.Steve Reinhardt
2008-01-02Fix formatting and comments in cache_impl.hhSteve Reinhardt
2008-01-01SPARC: Fix a bug where the TLB would match against the wrong entries.Gabe Black
2007-12-18Checkpointing: Fix a bug in the simulation script when restoring without stan...Ali Saidi
2007-12-16CPU: Update where the simple cpus read their cpu id from the thread context t...Ali Saidi
2007-12-11Fix minor bug in util/style.pySteve Reinhardt
2007-12-03X86: Update the parser reference output which has mysteriously changed again?Gabe Black
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