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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
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Commit message (
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Author
2005-06-04
BaseSystem -> System
Nathan Binkert
2005-06-04
more portable
Nathan Binkert
2005-06-03
Make m5.fast work
Nathan Binkert
2005-06-03
Bug fix & cleanup in config code.
Steve Reinhardt
2005-06-03
Additions/fixes for Tru64 syscall emulation.
Steve Reinhardt
2005-06-03
Make m5.fast work when there are no Trace.flags
Nathan Binkert
2005-06-02
Rename builds more descriptively:
Steve Reinhardt
2005-06-02
clean up command line stuff
Nathan Binkert
2005-06-02
Fix-up some config issues
Nathan Binkert
2005-06-02
update copyrights that are spit out on the console.
Nathan Binkert
2005-06-02
More de-SimpleScalarization of cache code.
Steve Reinhardt
2005-06-02
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
Steve Reinhardt
2005-06-01
Change lru/iic parameter checks for licensing.
Erik Hallnor
2005-06-01
Get rid of unused sim/int_stats.* files.
Steve Reinhardt
2005-06-01
Rename sim/universe.{cc,hh} to root.{cc,hh} (since the
Steve Reinhardt
2005-06-01
Standardize clock parameter names to 'clock'.
Steve Reinhardt
2005-06-01
Get rid of obsolete simobj/SConscript
Steve Reinhardt
2005-06-01
A few more config updates. Works with regression now.
Steve Reinhardt
2005-05-29
Major cleanup of python config code.
Steve Reinhardt
2005-05-28
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
Steve Reinhardt
2005-05-28
ns_gige_reg.h, ns_gige.cc:
Lisa Hsu
2005-05-26
Added copyright.
Kevin Lim
2005-05-25
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
Steve Reinhardt
2005-05-24
Little debugging things.
Steve Reinhardt
2005-05-20
Update mem trace reader params.
Steve Reinhardt
2005-05-20
Minor changes to get new cpu to compile with FULL_SYSTEM.
Steve Reinhardt
2005-05-19
Fix up code for initial release. The main bug that remains is properly forwa...
Kevin Lim
2005-05-17
Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/current/m5
Kevin Lim
2005-05-15
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
Steve Reinhardt
2005-05-15
Fix "no supplier" bug.
Steve Reinhardt
2005-05-14
More cleanup of fetch code.
Steve Reinhardt
2005-05-13
Add mem_trace parameter to BaseCache.
Steve Reinhardt
2005-05-13
panic vs fatal fixes in bus.cc
Steve Reinhardt
2005-05-12
Force pipeline drain on first instruction of async interrupt handler.
Steve Reinhardt
2005-05-12
Get rid of unused SMT code from FullCPU.
Steve Reinhardt
2005-05-09
Add definitions for memory trace writers.
Steve Reinhardt
2005-05-04
Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/current/m5
Kevin Lim
2005-05-03
Add support for dedicated 1GHz Simple CPU
Ron Dreslinski
2005-05-03
Large update of several parts of my code. The most notable change is the inc...
Kevin Lim
2005-05-02
Fix ethernet configuration
Nathan Binkert
2005-05-02
Skip calibrate delay again.
Nathan Binkert
2005-05-02
Make sinic work with mpy
Nathan Binkert
2005-05-02
workaround configuration bug in tick is ps.
Nathan Binkert
2005-05-02
Improve checkpointing of ethernet packets a bit.
Nathan Binkert
2005-05-02
Better configurations for checkpointing. Add more NIC options.
Nathan Binkert
2005-05-02
Make sure to just do the dma No Allocation on reads
Ron Dreslinski
2005-05-02
Add environment parameter for Allocation policy of DMA's
Ron Dreslinski
2005-05-02
Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
Kevin Lim
2005-04-30
Merge zizzer:/z/m5/Bitkeeper/m5
Ron Dreslinski
2005-04-30
Handle no_allocates as needing the response in miss_queue, like uncacheables
Ron Dreslinski
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