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AgeCommit message (Expand)Author
2017-10-13cpu-o3: Check predication before the SQ size for a debug printNikos Nikoleris
2017-10-13cpu-o3: Avoid early checker verification for store conditionalsNikos Nikoleris
2017-10-05tests: Fix path for module imports in ARM system configs againCurtis Dunham
2017-10-05misc: Add util/packet_pb2.py to .gitignore.Gabe Black
2017-10-05misc: Use a Makefile to ensure util/packet_pb2.py is up to date.Gabe Black
2017-10-05misc: When building packet_pb2.py, don't assume a particular CWD.Gabe Black
2017-10-05misc: Make decode_packet_trace.py print the new master ID fields.Gabe Black
2017-10-05misc: Small style fix in _EncodeVarint32.Gabe Black
2017-10-05misc: Rename the (De|En)codeVarint function _(De|En)codeVarint32.Gabe Black
2017-10-05misc: Fix the indentation in DecodeVarint in util/protolib.py.Gabe Black
2017-10-04tlm: Elastic Trace Example with L2 Cache AddedMatthias Jung
2017-09-28sim-se: Fix mremap for downward growing mmap regionsRico Amslinger
2017-09-27arch-x86: fix CondInst decoding for MOV to Control RegistersBjoern A. Zeeb
2017-09-27arch: change panic for Vector traceData to warn_onceBjoern A. Zeeb
2017-09-27sim: make compile on FreeBSD prior to 11Bjoern A. Zeeb
2017-09-26util: Make dot_writer ignore NULL simobjects.Gabe Black
2017-09-26dev: Make the IDE controller handle NULL simobject pointers.Gabe Black
2017-09-26sim: Add a get_config_as_dict to the NullSimObject class.Gabe Black
2017-09-26sim: Don't add the NULL SimObject as a child of other SimObjects.Gabe Black
2017-09-26misc: Make the m5 utilities writefile command accept a host path.Gabe Black
2017-09-26sim: Give the NullSimObject singleton a _name.Gabe Black
2017-09-26sim: Add a NullSimObject.descendants function.Gabe Black
2017-09-26sim: Add a clear_parent function to NullSimObject.Gabe Black
2017-09-26sim: Check the SimObjectVector.has_parent function to use the "any" function.Gabe Black
2017-09-26sim: Only consider non-NULL elements in SimObjectVector.has_parent.Gabe Black
2017-09-26sim: Add a set_parent to NullSimObject which does nothing.Gabe Black
2017-09-25mem: Fill the new packet ID fields with master IDs when tracing packets.Gabe Black
2017-09-25mem: Add a "map" of packet IDs to strings in probe traces.Gabe Black
2017-09-25mem: Trace the request master ID in the MemTraceProbe.Gabe Black
2017-09-25mem: Record the request master ID in the PacketInfo structure.Gabe Black
2017-09-25dev, virtio: Improvements to diod process handlingAnouk Van Laer
2017-09-21alpha: Move some initialization logic from loadState into unserialize.Gabe Black
2017-09-21sim: Stop using loadState in the Root SimObject.Gabe Black
2017-09-20kvm: arm: Get rid of functions which just wrap the subclasses version.Gabe Black
2017-09-11tlm: Don't set SystemC time resolutionMatthias Jung
2017-09-11stats: Move the swpipl function into the Alpha kernel stats.Gabe Black
2017-09-11stats: Get rid of some kernel stats related cruft.Gabe Black
2017-09-06cpu: Fix bi-mode branch predictor thresholdsRico Amslinger
2017-09-01cpu-minor: Fix for addr range coverage calculationPau Cabre
2017-08-31scons: bump required python version to 2.7 to support pybind11Paul Rosenfeld
2017-08-30arch-arm: Only increment SW PMU counters on writes to PMSWINCJose Marinho
2017-08-30arch-arm: Add missing override keywords in fault.hhAndreas Sandberg
2017-08-30arch-x86: Add missing override in the X86 TLBAndreas Sandberg
2017-08-30arch-sparc: Add a FaultVals instantiation for VecDisabledAndreas Sandberg
2017-08-30arch-alpha: Add missing overridesAndreas Sandberg
2017-08-30python: Make GlobalExitEvent.getCode() return an intAndreas Sandberg
2017-08-30cpu-o3: fix data pkt initialization for split loadMatthias Hille
2017-08-28x86: Use the new CondInst format for moves to/from control registers.Gabe Black
2017-08-28x86: Add a "CondInst" format for conditionally decoded instructions.Gabe Black
2017-08-12dev: Fix an IDE error check.Gabe Black