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2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
Virtualized CPUs and the fastmem mode of the atomic CPU require direct access to physical memory. We currently require caches to be disabled when using them to prevent chaos. This is not ideal when switching between hardware virutalized CPUs and other CPU models as it would require a configuration change on each switch. This changeset introduces a new version of the atomic memory mode, 'atomic_noncaching', where memory accesses are inserted into the memory system as atomic accesses, but bypass caches. To make memory mode tests cleaner, the following methods are added to the System class: * isAtomicMode() -- True if the memory mode is 'atomic' or 'direct'. * isTimingMode() -- True if the memory mode is 'timing'. * bypassCaches() -- True if caches should be bypassed. The old getMemoryMode() and setMemoryMode() methods should never be used from the C++ world anymore.
2013-02-15cpu: Refactor memory system checksAndreas Sandberg
CPUs need to test that the memory system is in the right mode in two places, when the CPU is initialized (unless it's switched out) and on a drainResume(). This led to some code duplication in the CPU models. This changeset introduces the verifyMemoryMode() method which is called by BaseCPU::init() if the CPU isn't switched out. The individual CPU models are responsible for calling this method when resuming from a drain as this code is CPU model specific.
2013-02-15config: Remove O3 dependenciesAndreas Sandberg
The default cache configuration script currently import the O3_ARM_v7a model configuration, which depends on the O3 CPU. This breaks if gem5 has been compiled without O3 support. This changeset removes the dependency by only importing the model if it is requested by the user. As a bonus, it actually removes some code duplication in the configuration scripts.
2013-02-15config: Move CPU handover logic to m5.switchCpus()Andreas Sandberg
CPU switching consists of the following steps: 1. Drain the system 2. Switch out old CPUs (cpu.switchOut()) 3. Change the system timing mode to the mode the new CPUs require 4. Flush caches if switching to hardware virtualization 5. Inform new CPUs of the handover (cpu.takeOverFrom()) 6. Resume the system m5.switchCpus() previously only did step 2 & 5. Since information about the new processors' memory system requirements is now exposed, do all of the steps above. This patch adds automatic memory system switching and flush (if needed) to switchCpus(). Additionally, it adds optional draining to switchCpus(). This has the following implications: * changeToTiming and changeToAtomic are no longer needed, so they have been removed. * changeMemoryMode is only used internally, so it is has been renamed to be private. * switchCpus requires a reference to the system containing the CPUs as its first parameter. WARNING: This changeset breaks compatibility with existing configuration scripts since it changes the signature of m5.switchCpus().
2013-02-15config: Cleanup CPU configurationAndreas Sandberg
The CPUs supported by the configuration scripts used to be hard-coded. This was not ideal for several reasons. For example, the configuration scripts depend on all CPU models even though only a subset might have been compiled. This changeset adds a new module to the configuration scripts that automatically discovers the available CPU models from the compiled SimObjects. As a nice bonus, the use of introspection allows us to automatically generate a list of available CPU models suitable for printing. This list is augmented with the Python doc string from the underlying class if available.
2013-02-15cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchyAndreas Sandberg
Checker CPUs currently don't inherit from the CheckerCPU in the Python object hierarchy. This has two consequences: * It makes CPU model discovery from the Python world somewhat complicated as there is no way of testing if a CPU is a checker. * Parameters are duplicated in the checker configuration specification. This changeset makes all checker CPUs inherit from the base checker CPU class.
2013-02-15cpu: Add CPU metadata om the Python classesAndreas Sandberg
The configuration scripts currently hard-code the requirements of each CPU. This is clearly not optimal as it makes writing new configuration scripts painful and adding new CPU models requires existing scripts to be updated. This patch adds the following class methods to the base CPU and all relevant CPUs: * memory_mode -- Return a string describing the current memory mode (invalid/atomic/timing). * require_caches -- Does the CPU model require caches? * support_take_over -- Does the CPU support CPU handover?
2013-02-15arm: fix some fp comparisons that worked by accident.Ali Saidi
The explict tests in the follwing fp comparison operations were incorrect as they checked for only signaling NaNs and not quite-NaNs as well. When compiled with gcc, the comparison generates a fp exception that causes the FE_INVALID flag to be set and we check for it, so even though the check was incorrect, the correct exception was set. With clang this behavior seems to not occur. The checks are updated to test for nans and the behavior is now correct with both clang and gcc.
2013-02-15cpu: include set in o3/commit_impl.Ali Saidi
While the majority of compilers seemed to pickup set from else where, one version of gcc 4.7 complains, so explictly add it.
2013-02-15ARM: Fix an issue with clang generating wrong code.Ali Saidi
Clang generated executables would enter the if condition when it wasn't supposted to, resulting in the wrong simulated behavior. Implementing the operation this way is a bit faster anyway.
2013-02-15cpu: fix case with o3 cpu blocking and unblocking decode in cycleAli Saidi
Fix a case in the O3 CPU where the decode stage blocks and unblocks in a single cycle sending both signals to fetch which causes an assert or worse. The previous check could never work before since the status was set to Blocked before a test for the status being Unblocking was executed.
2013-02-15cpu: Fix a livelock in the o3 cpu.Ali Saidi
Check if an instruction just enabled interrupts and we've previously had an interrupt pending that was not handled because interrupts were subsequently disabled before the pipeline reached a place to handle the interrupt. In that case squash now to make sure the interrupt is handled.
2013-02-10base: Add support for newer versions of IPythonAndreas Sandberg
IPython is used for the interactive gem5 shell if it exists. IPython made API changes in version 0.11. This patch adds support for IPython version 0.11 and above. --HG-- extra : rebase_source : 5388d0919adb58d97f49a1a637db48cba61283a3
2013-02-14Ruby: Fix compilation errors on gcc 4.7 and clang 3.2Andreas Hansson
This patch fixes a few (recently added) errors that prevented gem5 from compiling on more recent versions of gcc and clang.
2013-02-10regressions: update stats due to changes to rubyNilay Vaish
2013-02-10ruby: MI protocol: add a missing transitionNilay Vaish
The transition for state MII and event Store was found missing during testing. The transition is being added. The controller will not stall the Store request in state MII
2013-02-10ruby: enable multiple clock domainsNilay Vaish
This patch allows ruby to have multiple clock domains. As I understand with this patch, controllers can have different frequencies. The entire network needs to run at a single frequency. The idea is that with in an object, time is treated in terms of cycles. But the messages that are passed from one entity to another should contain the time in Ticks. As of now, this is only true for the message buffers, but not for the links in the network. As I understand the code, all the entities in different networks (simple, garnet-fixed, garnet-flexible) should be clocked at the same frequency. Another problem is that the directory controller has to operate at the same frequency as the ruby system. This is because the memory controller does not make use of the Message Buffer, and instead implements a buffer of its own. So, it has no idea of the frequency at which the directory controller is operating and uses ruby system's frequency for scheduling events.
2013-02-10ruby: replace Time with Cycles (final patch in the series)Nilay Vaish
This patch is as of now the final patch in the series of patches that replace Time with Cycles.This patch further replaces Time with Cycles in Sequencer, Profiler, different protocols and related entities. Though Time has not been completely removed, the places where it is in use seem benign as of now.
2013-02-10ruby: replace Time with Cycles in garnet fixed and flexibleNilay Vaish
2013-02-10ruby: replace Time with Tick in replacement policy classesNilay Vaish
2013-02-10ruby: convert block size, memory size to unsignedNilay Vaish
2013-02-10ruby: replace Time with Cycles in MessageBufferNilay Vaish
2013-02-10ruby: replace Time with Cycles in Memory ControllerNilay Vaish
2013-02-10ruby: Replace Time with Cycles in SequencerMessageNilay Vaish
2013-02-10ruby: replace Time with Cycles in Message classNilay Vaish
Concomitant changes are being committed as well, including the io operator<< for the Cycles class.
2013-02-10ruby: replaces Time with Cycles in many placesNilay Vaish
The patch started of with replacing Time with Cycles in the Consumer class. But to get ruby to compile, the rest of the changes had to be carried out. Subsequent patches will further this process, till we completely replace Time with Cycles.
2013-02-10base: add some mathematical operators to Cycles classNilay Vaish
2013-02-10ruby: modifies histogram add() functionNilay Vaish
This patch modifies the Histogram class' add() function so that it can add linear histograms as well. The function assumes that the left end point of the ranges of the two histograms are the same. It also assumes that when the ranges of the two histogram are changed to accomodate an element not in the range, the factor used in changing the range is same for both the histograms. This function is then used in removing one of the calls to the global profiler*. The histograms for recording the delays incurred in processing different requests are now maintained by the controllers. The profiler adds these histograms when it needs to print the stats.
2013-02-10ruby: record fully busy cycle with in the controllerNilay Vaish
This patch does several things. First, the counter for fully busy cycles for a controller is now kept with in the controller, instead of being part of the profiler. Second, the topology class no longer keeps an array of controllers which was only used for printing stats. Instead, ruby system will now ask each controller to print the stats. Thirdly, the statistical variable for recording how many different types were created is being moved in to the controller from the profiler. Note that for printing, the profiler will collate results from different controllers.
2013-02-10base: Fix broken IPython argument handlingAndreas Sandberg
Prior to this changeset, we used to clear sys.argv before entering the IPython shell. This caused some versions of IPython to crash because they assume argv[0] to exist. The correct way of overriding the arguments passed to IPython is to set the argv keyword argument when initializing the shell.
2013-02-10config: Don't call sys.exit in interactive mode in run()Andreas Sandberg
The run() method in Simulation.py used to call sys.exit() when the simulator exits. This is undesirable when user has requested the simulator to be run in interactive mode since it causes the simulator to exit rather than entering the interactive Python environment.
2013-01-31sim: remove unused struct priority_compareNilay Vaish
2013-01-31ruby: correct computation of number of bits required for addressNilay Vaish
The number of bits required for an address was set to floorLog2(memory size). This is correct under the assumption that the memory size is a power of 2, which is not always true. Hence, floorLog2 is being replaced with ceilLog2.
2013-01-31mem: Add comments for the DRAM address decodingAndreas Hansson
This patch adds more verbose comments to explain the two different address mapping schemes of the DRAM controller.
2013-01-31stats: Update stats for regressions using SimpleDDR3Andreas Hansson
This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default.
2013-01-31mem: Add DDR3 and LPDDR2 DRAM controller configurationsAndreas Hansson
This patch moves the default DRAM parameters from the SimpleDRAM class to two different subclasses, one for DDR3 and one for LPDDR2. More can be added as we go forward. The regressions that previously used the SimpleDRAM are now using SimpleDDR3 as this is the most similar configuration.
2013-01-31mem: Add tTAW and tFAW to the SimpleDRAM modelAni Udipi
This patch adds two additional scheduling constraints to the DRAM controller model, to constrain the activation rate. The two metrics are determine the size of the activation window in terms of the number of activates and the minimum time required for that number of activates. This maps to current DDRx, LPDDRx and WIOx standards that have either tFAW (4 activate window) or tTAW (2 activate window) scheduling constraints.
2013-01-31mem: Separate out the different cases for DRAM bus busy timeAndreas Hansson
This patch changes how the data bus busy time is calculated such that it is delayed to the actual scheduling time of the request as opposed to being done as soon as possible. This patch changes a bunch of statistics, and the stats update is bundled together with the introruction of tFAW/tTAW and the named DRAM configurations like DDR3 and LPDDR2.
2013-01-28cache: remove drainManager because it's not usedAnthony Gutierrez
the cache drainManager is set but never cleared, this is because the cache itself does not need to be drained and thus never triggers a signalDrainDone(). because the drainManager variable is not used properly and does not appear to be necessary it has been removed with this patch.
2013-01-28merged 798c2cec8e37 and e96ff45795bcNilay Vaish
2013-01-28stats: Fix naming (BPredUnit to branchPred) for 20.parser ARM o3Andreas Hansson
This patch bumps the stats for 20.parser for ARM o3-timing to reflect a namechange of the branch predictor.
2013-01-28ruby: remove get_time()Nilay Vaish
This patch replaces get_time() in *.sm files with curCycle() which is now possible since controllers are clocked objects.
2013-01-28ruby: remove call to curCycle in panic()Nilay Vaish
The panic() function already prints the current tick value. This call to curCycle() is as such redundant. Since we are trying to move towards multiple clock domains, this call will print misleading time.
2013-01-24regressions: update stats due to branch predictor changesNilay Vaish
The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
2013-01-24branch predictor: move out of o3 and inorder cpusNilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
This patch moves the branch predictor files in the o3 and inorder directories to src/cpu/pred. This allows sharing the branch predictor across different cpu models. This patch was originally posted by Timothy Jones in July 2010 but never made it to the repository. --HG-- rename : src/cpu/o3/bpred_unit.cc => src/cpu/pred/bpred_unit.cc rename : src/cpu/o3/bpred_unit.hh => src/cpu/pred/bpred_unit.hh rename : src/cpu/o3/bpred_unit_impl.hh => src/cpu/pred/bpred_unit_impl.hh rename : src/cpu/o3/sat_counter.hh => src/cpu/pred/sat_counter.hh
2013-01-22o3 cpu: fix zero reg problemAndrea Pellegrini
There was an issue w/ the rename logic, which would assign a previous physical register to the ZeroReg architectural register in x86. This issue was giving problems for instructions squashed in threads w/ ID different from 0, sometimes allowing non-mispredicted instructions to obtain a value different from zero when reading the zeroReg.
2013-01-22x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switchNilay Vaish
The changes made by the changeset 270c9a75e91f do not work well with switching of cpus. The problem is that decoder for the old thread context holds state that is not taken over by the new decoder. This patch adds a takeOverFrom() function to Decoder class in each ISA. Except for x86, functions in other ISAs are blank. For x86, the function copies state from the old decoder to the new decoder.
2013-01-21scons: Disable protobuf if pkg-config and CheckLib failsAndreas Hansson
This patch changes the use of pkg-config such that protobuf is still evaluated with CheckLib even if it fails. This is to allow setups where libprotobuf is available, but not configured through protobuf. Moreover, if CheckLib fails to use libprotobuf then all the tracing is disabled, but scons is allowed to continue with a warning.
2013-01-19O3 IEW: Make incrWb and decrWb clearerJoel Hestness
Move the increment/decrement of wbOutstanding outside of the comparison in incrWb and decrWb in the IEW. This also fixes a compiler bug with gcc 4.4.7, which incorrectly optimizes "-- ==" as "-=".
2013-01-17ruby: remove calls to g_system_ptr->getTime()Nilay Vaish
This patch further removes calls to g_system_ptr->getTime() where ever other clocked objects are available for providing current time.