Age | Commit message (Collapse) | Author |
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SConscript:
Remove efence option from automatically being used.
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dev/tsunami_cchip.cc:
add a fake register to tsunami that we can do 32bit reads to.
Warn on access.
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extra : convert_revision : d87860f3b527528151c23431556039bca6e12945
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into zizzer.eecs.umich.edu:/z/stever/bk/m5
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util/tracediff:
Fix bug (used += instead of .= for string concatenation in Perl...
wrong language!).
Also updated for new config (s/Universe/root/).
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address calculation and memory access portions separately.
Not currently used by any CPU models, but Kevin says he needs this.
Also clean up handling of execution tracing for memory accesses
(move it all into isa_desc and out of CPU models).
Got rid of some ancient unused code too.
arch/alpha/isa_desc:
Add execute() methods to EAComp and MemAcc portions of memory
access instructions, to allow CPU models to execute the effective
address calculation and memory access portions separately.
Requires the execution context to remember the effective address
across the two invocations. Added setEA() and getEA() methods to
execution context to support this. A model that does not use the
split execution model can panic if these methods are called.
Also added hook to call traceData->setAddr() after EA computation
on any load or store operation.
arch/isa_parser.py:
Call traceData->setData() on memory writes (stores).
cpu/simple_cpu/simple_cpu.cc:
Get rid of unused code.
cpu/simple_cpu/simple_cpu.hh:
Add (non-functional) setEA() and getEA() methods for new
split memory access execution support.
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extra : convert_revision : bc2d2c758c4ca753812b9fa81f21038e55929ff0
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get rid of the alias for true to True and false to False to keep
consistent python syntax.
util/stats/info.py:
Fix typo
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extra : convert_revision : e69588a8de52424e043315e70008ca3a3ede7d5b
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dev/simconsole.cc:
sim/universe.cc:
isValid isn't compatible with new python stuff, so whack it.
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objects/AlphaConsole.mpy:
objects/AlphaTLB.mpy:
objects/BadDevice.mpy:
objects/BaseCPU.mpy:
objects/BaseCache.mpy:
objects/BaseSystem.mpy:
objects/Bus.mpy:
objects/CoherenceProtocol.mpy:
objects/Device.mpy:
objects/DiskImage.mpy:
objects/Ethernet.mpy:
objects/Ide.mpy:
objects/IntrControl.mpy:
objects/MemTest.mpy:
objects/Pci.mpy:
objects/PhysicalMemory.mpy:
objects/Platform.mpy:
objects/Process.mpy:
objects/Repl.mpy:
objects/Root.mpy:
objects/SimConsole.mpy:
objects/SimpleDisk.mpy:
objects/Tsunami.mpy:
objects/Uart.mpy:
simobj now requires a type= line if it is actually intended
to be a type
sim/pyconfig/SConscript:
keep track of the filename of embedded files for better
error messages.
sim/pyconfig/m5config.py:
Add support for the trickery done with the compiler to get the
simobj language feature added to the importer.
fix the bug that gave objects the wrong name in error messages.
test/genini.py:
Globals have been fixed and use execfile
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extra : convert_revision : b74495fd6f3479a87ecea7f1234ebb6731279b2b
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objects/BaseCache.mpy:
add all the Split parameters to the BaseCache simobj.
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head in my mad prelim rush.
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all but tlaser_node.cc dependence on tlaserreg.h
dev/tsunami_io.cc:
dev/tsunamireg.h:
removed tlaserreg.h
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into zizzer.eecs.umich.edu:/.automount/zamp/z/ktlim2/m5-patched/m5-new
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into zamp.eecs.umich.edu:/z/ktlim2/m5-patched/m5-new
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objects/Root.mpy:
add checkpointing as a parameter to the root object.
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extra : convert_revision : 3b809ebd776c8a9256a4ad6f8783cd96ab5cb1b3
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that we can handle more uncached access (we will get some from multiple processors)
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base/stats/events.cc:
cast this to an unsigned long long to make the compiler happy
on 64-bit platforms.
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extra : convert_revision : e893d21bb228cbfb0c23adb7c4eeb1f62209ca1c
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Fix the nat config.
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extra : convert_revision : 22bd4f20408371b644b51fd8d6b79486e1e5a59b
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into ziff.eecs.umich.edu:/z/binkertn/research/m5/latest
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extra : convert_revision : 47fe06540907f6810cd1bccfc96a8705fd38c4ba
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/new_config
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extra : convert_revision : 8c87cd948d501b1fc58d57f1f505d1f72725ecde
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dev/pktfifo.cc:
Make it so that we don't unserialize the size of the fifo, clobering the fact that we were trying to make it bigger, and leading to a misleading config.out that states the un-overwritten max_size.
Perhaps this should instead be a panic if the size (amount that was serialized) is bigger than the maxsize that was assigned by the configuration file.
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arch/alpha/pseudo_inst.cc:
rename the context for consistency.
sim/pyconfig/m5config.py:
Add a ParamContext class so that param contexts work with
the new config stuff.
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cleaned up stability code and wrote some better help for stats.py
fixed sample bug in info.py
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/sinic.cc:
dev/sinic.hh:
add total bandwidth/packets/bytes stats
util/stats/info.py:
fixed samples bug
util/stats/stats.py:
cleaned up stability code and wrote a bit better help
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but prints everything else.
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into zamp.eecs.umich.edu:/z/ktlim2/m5-patched/m5-new
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serialization)
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dev/pktfifo.cc:
fix unserialization. calling resize on a list just sticks
uninitialized garbage into the list.
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add a Sampler configuration for the P4
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objects/Pci.mpy:
specify that the value is a long so that it is not
interpreted as a negative value.
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into zamp.eecs.umich.edu:/z/ktlim2/m5
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into zamp.eecs.umich.edu:/z/ktlim2/m5-patched/m5-new
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sim/pyconfig/m5config.py:
put panic, AddToPath, and Import here so they're always available.
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