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2015-03-02mem: Downstream components consumes new crossbar delaysMarco Balboni
This patch makes the caches and memory controllers consume the delay that is annotated to a packet by the crossbar. Previously many components simply threw these delays away. Note that the devices still do not pay for these delays.
2015-03-02mem: Move crossbar default latencies to subclassesAndreas Hansson
This patch introduces a few subclasses to the CoherentXBar and NoncoherentXBar to distinguish the different uses in the system. We use the crossbar in a wide range of places: interfacing cores to the L2, as a system interconnect, connecting I/O and peripherals, etc. Needless to say, these crossbars have very different performance, and the clock frequency alone is not enough to distinguish these scenarios. Instead of trying to capture every possible case, this patch introduces dedicated subclasses for the three primary use-cases: L2XBar, SystemXBar and IOXbar. More can be added if needed, and the defaults can be overridden.
2015-03-02mem: Add crossbar latenciesMarco Balboni
This patch introduces latencies in crossbar that were neglected before. In particular, it adds three parameters in crossbar model: front_end_latency, forward_latency, and response_latency. Along with these parameters, three corresponding members are added: frontEndLatency, forwardLatency, and responseLatency. The coherent crossbar has an additional snoop_response_latency. The latency of the request path through the xbar is set as --> frontEndLatency + forwardLatency In case the snoop filter is enabled, the request path latency is charged also by look-up latency of the snoop filter. --> frontEndLatency + SF(lookupLatency) + forwardLatency. The latency of the response path through the xbar is set instead as --> responseLatency. In case of snoop response, if the response is treated as a normal response the latency associated is again --> responseLatency; If instead it is forwarded as snoop response we add an additional variable + snoopResponseLatency and the latency associated is --> snoopResponseLatency; Furthermore, this patch lets the crossbar progress on the next clock edge after an unused retry, changing the time the crossbar considers itself busy after sending a retry that was not acted upon.
2015-03-02dev, arm: Clean up PL011 and rewrite interrupt handlingAndreas Sandberg
The ARM PL011 UART model didn't clear and raise interrupts correctly. This changeset rewrites the whole interrupt handling and makes it both simpler and fixes several cases where the correct interrupts weren't raised or cleared. Additionally, it cleans up many other aspects of the code.
2015-03-02arm: Share a port for the two table walker objectsAndreas Hansson
This patch changes how the MMU and table walkers are created such that a single port is used to connect the MMU and the TLBs to the memory system. Previously two ports were needed as there are two table walker objects (stage one and stage two), and they both had a port. Now the port itself is moved to the Stage2MMU, and each TableWalker is simply using the port from the parent. By using the same port we also remove the need for having an additional crossbar joining the two ports before the walker cache or the L2. This simplifies the creation of the CPU cache topology in BaseCPU.py considerably. Moreover, for naming and symmetry reasons, the TLB walker port is connected through the stage-one table walker thus making the naming identical to x86. Along the same line, we use the stage-one table walker to generate the master id that is used by all TLB-related requests.
2015-03-02arm: Remove unnecessary dependencies between AArch64 FP instructionsGiacomo Gabrielli
2015-03-02cpu: o3 register renaming request handling improvedRekai
Now, prior to the renaming, the instruction requests the exact amount of registers it will need, and the rename_map decides whether the instruction is allowed to proceed or not.
2015-03-02mem: Tidy up the cache debug messagesAndreas Hansson
Avoid redundant inclusion of the name in the DPRINTF string.
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
This patch fixes a long-standing isue with the port flow control. Before this patch the retry mechanism was shared between all different packet classes. As a result, a snoop response could get stuck behind a request waiting for a retry, even if the send/recv functions were split. This caused message-dependent deadlocks in stress-test scenarios. The patch splits the retry into one per packet (message) class. Thus, sendTimingReq has a corresponding recvReqRetry, sendTimingResp has recvRespRetry etc. Most of the changes to the code involve simply clarifying what type of request a specific object was accepting. The biggest change in functionality is in the cache downstream packet queue, facing the memory. This queue was shared by requests and snoop responses, and it is now split into two queues, each with their own flow control, but the same physical MasterPort. These changes fixes the previously seen deadlocks.
2015-03-02mem: Fix prefetchSquash + memInhibitAsserted bugAli Jafri
This patch resolves a bug with hardware prefetches. Before a hardware prefetch is sent towards the memory, the system generates a snoop request to check all caches above the prefetch generating cache for the presence of the prefetth target. If the prefetch target is found in the tags or the MSHRs of the upper caches, the cache sets the prefetchSquashed flag in the snoop packet. When the snoop packet returns with the prefetchSquashed flag set, the prefetch generating cache deallocates the MSHR reserved for the prefetch. If the prefetch target is found in the writeback buffer of the upper cache, the cache sets the memInhibit flag, which signals the prefetch generating cache to expect the data from the writeback. When the snoop packet returns with the memInhibitAsserted flag set, it marks the allocated MSHR as inService and waits for the data from the writeback. If the prefetch target is found in multiple upper level caches, specifically in the tags or MSHRs of one upper level cache and the writeback buffer of another, the snoop packet will return with both prefetchSquashed and memInhibitAsserted set, while the current code is not written to handle such an outcome. Current code checks for the prefetchSquashed flag first, if it finds the flag, it deallocates the reserved MSHR. This leads to assert failure when the data from the writeback appears at cache. In this fix, we simply switch the order of checks. We first check for memInhibitAsserted and then for prefetch squashed.
2015-03-02cpu: Add a PC-value to the traffic generator requestsStephan Diestelhorst
Have the traffic generator add its masterID as the PC address to the requests. That way, prefetchers (and other components) that use a PC for request classification will see per-tester streams of requests. This enables us to test strided prefetchers with the memchecker, too.
2015-03-02tests: Run regression timeout as foregroundAndreas Hansson
Allow the user to send signals such as Ctrl C to the gem5 runs. Note that this assumes coreutils >= 8.13, which aligns with Ubuntu 12.04 and RHE6.
2015-03-02arm: Don't truncate 16-bit ASIDs to 8 bitsAndreas Sandberg
The ISA code sometimes stores 16-bit ASIDs as 8-bit unsigned integers and has a couple of inverted checks that mask out the high 8 bits of an ASID if 16-bit ASIDs have been /enabled/. This changeset fixes both of those issues.
2015-03-02arm: Correctly access the stack pointer in GDBAndreas Sandberg
We curently use INTREG_X31 instead of INTREG_SPX when accessing the stack pointer in GDB. gem5 normally uses INTREG_SPX to access the stack pointer, which gets mapped to the stack pointer corresponding (INTREG_SPn) to the current exception level. This changeset updates the GDB interface to use SPX instead of X31 (which is always zero) when transfering CPU state to gdb.
2015-03-02arm: Fix broken page table permissions checks in remote GDBAndreas Sandberg
The remote GDB interface currently doesn't check if translations are valid before reading memory. This causes a panic when GDB tries to access unmapped memory (e.g., when getting a stack trace). There are two reasons for this: 1) The function used to check for valid translations (virtvalid()) doesn't work and panics on invalid translations. 2) The method in the GDB interface used to test if a translation is valid (RemoteGDB::acc) always returns true regardless of the return from virtvalid(). This changeset fixes both of these issues.
2015-02-26Ruby: Update backing store option to propagate through to all RubyPortsJason Power
Previously, the user would have to manually set access_backing_store=True on all RubyPorts (Sequencers) in the config files. Now, instead there is one global option that each RubyPort checks on initialization. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
2015-02-16config: Add memcheck stress testAndreas Hansson
This is a rather unfortunate copy of the memtest.py example script, that actually stresses the system with true sharing as opposed to the false sharing of the MemTest. To do so it uses TrafficGen instances to generate the reads/writes, and MemCheckerMonitor combined with the MemChecker to check the validity of the read/written values. As a bonus, this script also enables the addition of prefetchers, and the traffic is created to have a mix of random addresses and linear strides. We use the TaggedPrefetcher since the packets do not have a request with a PC. At the moment the code is almost identical to the memtest.py script, and no effort has been made to factor out the construction of the tree. The challenge is that the instantiation and connection of the testers and monitors is done as part of the tree building.
2015-02-16cpu: TrafficGen sinks snoops without complainingAndreas Hansson
To be able to use the TrafficGen in a system with caches we need to allow it to sink incoming snoop requests. By default the master port panics, so silently ignore any snoops.
2015-02-16mem: Fix initial value problem with MemCheckerStephan Diestelhorst
In highly loaded cases, reads might actually overlap with writes to the initial memory state. The mem checker needs to detect such cases and permit the read reading either from the writes (what it is doing now) or read from the initial, unknown value. This patch adds this logic.
2015-02-16dev: Fix undefined behaviuor in i8254xGBeAndreas Hansson
This patch fixes a rather unfortunate oversight where the annotation pointer was used even though it is null. Somehow the code still works, but UBSan is rather unhappy. The use is now guarded, and the variable is initialised in the constructor (as well as init()).
2015-02-16arm: Wire up the GIC with the platform in the base classAndreas Sandberg
Move the (common) GIC initialization code that notifies the platform code of the new GIC to the base class (BaseGic) instead of the Pl390 implementation.
2015-02-16mem: mmap the backing store with MAP_NORESERVEAndreas Hansson
This patch ensures we can run simulations with very large simulated memories (at least 64 TB based on some quick runs on a Linux workstation). In essence this allows us to efficiently deal with sparse address maps without having to implement a redirection layer in the backing store. This opens up for run-time errors if we eventually exhausts the hosts memory and swap space, but this should hopefully never happen.
2015-02-16mem: Use the range cache for lookup as well as accessAndreas Hansson
This patch changes the range cache used in the global physical memory to be an iterator so that we can use it not only as part of isMemAddr, but also access and functionalAccess. This matches use-cases where a core is using the atomic non-caching memory mode, and repeatedly calls isMemAddr and access. Linux boot on aarch32, with a single atomic CPU, is now more than 30% faster when using "--fastmem" compared to not using the direct memory access.
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
Finally took the plunge and made this apply to all ISAs, not just ARM.
2015-01-16config: add --root-device machine parameterCurtis Dunham
In case /dev/sda1 is not actually the boot partition for an image, we can override it on the command line or in a benchmark definition.
2015-02-16arm: Merge ISA files with pseudo instructionsAndreas Sandberg
This changeset moves the pseudo instructions used to signal unknown instructions and unimplemented instructions to the same source files as the decoder fault.
2015-02-16cpu: add support for outputing a protobuf formatted CPU traceAli Saidi
Doesn't support x86 due to static instruction representation. --HG-- rename : src/cpu/CPUTracers.py => src/cpu/InstPBTrace.py
2015-02-11mem: Clarification of packet crossbar timingsMarco Balboni
This patch clarifies the packet timings annotated when going through a crossbar. The old 'firstWordDelay' is replaced by 'headerDelay' that represents the delay associated to the delivery of the header of the packet. The old 'lastWordDelay' is replaced by 'payloadDelay' that represents the delay needed to processing the payload of the packet. For now the uses and values remain identical. However, going forward the payloadDelay will be additive, and not include the headerDelay. Follow-on patches will make the headerDelay capture the pipeline latency incurred in the crossbar, whereas the payloadDelay will capture the additional serialisation delay.
2015-02-11mem: Clarify usage of latency in the cacheMarco Balboni
This patch adds some much-needed clarity in the specification of the cache timing. For now, hit_latency and response_latency are kept as top-level parameters, but the cache itself has a number of local variables to better map the individual timing variables to different behaviours (and sub-components). The introduced variables are: - lookupLatency: latency of tag lookup, occuring on any access - forwardLatency: latency that occurs in case of outbound miss - fillLatency: latency to fill a cache block We keep the existing responseLatency The forwardLatency is used by allocateInternalBuffer() for: - MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer); - MSHR allocateMissBuffer (cacheable miss in MSHR queue); - MSHR allocateUncachedReadBuffer (unchached read allocated in MSHR queue) It is our assumption that the time for the above three buffers is the same. Similarly, for snoop responses passing through the cache we use forwardLatency.
2015-02-11style: Fix broken m5format commandAndreas Sandberg
The m5format command didn't actually work due to parameter handling issues and missing language detection. This changeset fixes those issues and cleans up some of the code to shared between the style checker and the format checker.
2015-02-11style: Fix incorrect style checker option nameAndreas Sandberg
The style used to support the option -w to automatically fix white space issues. However, this option was actually wired up to fix all styles issues the checker encountered. This changeset cleans up the code that handles automatic fixing and adds an option to fix all issues, and separate options for white spaces and include ordering.
2015-02-11config: Revamp memtest to allow testers on any levelAndreas Hansson
This patch revamps the memtest example script and allows for the insertion of testers at any level in the cache hierarchy. Previously all created topologies placed testers only at the very top, and the tree was thus entirely symmetric. With the changes made, it is possible to not only place testers at the leaf caches (L1), but also to connect testers at the L2, L3 etc. As part of the changes the object hierarchy is also simplified to ensure that the visual representation from the DOT printing looks sensible. Using SubSystems to group the objects is one of the key features.
2015-02-11stats: Bump the MemTest regression statsAndreas Hansson
Reflect changes in the tester behaviour.
2015-02-11cpu: Tidy up the MemTest and make false sharing more obviousAndreas Hansson
The MemTest class really only tests false sharing, and as such there was a lot of old cruft that could be removed. This patch cleans up the tester, and also makes it more clear what the assumptions are. As part of this simplification the reference functional memory is also removed. The regression configs using MemTest are updated to reflect the changes, and the stats will be bumped in a separate patch. The example config will be updated in a separate patch due to more extensive re-work. In a follow-on patch a new tester will be introduced that uses the MemChecker to implement true sharing.
2015-02-11sim: Move the BaseTLB to src/arch/generic/Andreas Sandberg
The TLB-related code is generally architecture dependent and should live in the arch directory to signify that. --HG-- rename : src/sim/BaseTLB.py => src/arch/generic/BaseTLB.py rename : src/sim/tlb.cc => src/arch/generic/tlb.cc rename : src/sim/tlb.hh => src/arch/generic/tlb.hh
2015-02-11base: Add compiler macros to add deprecation warningsAndreas Sandberg
Gcc and clang both provide an attribute that can be used to flag a function as deprecated at compile time. This changeset adds a gem5 compiler macro for that compiler feature. The macro can be used to indicate that a legacy API within gem5 has been deprecated and provide a graceful migration to the new API.
2015-02-11base: Do not dereference NULL in CompoundFlag creationAndreas Hansson
This patch fixes the CompoundFlag constructor, ensuring that it does not dereference NULL. Doing so has undefined behaviuor, and both clang and gcc's undefined-behaviour sanitiser was rather unhappy.
2015-02-11dev: Remove unused system pointer in the Platform base classAndreas Sandberg
The Platform base class contains a pointer to an instance of the System which is never initialized. This can lead to subtle bugs since some architecture-specific platform implementations contain their own system pointer which is normally used. However, if the platform is accessed through a pointer to its base class, the dangling pointer will be used instead.
2015-02-06cpu: Idle CPU status logic revisedAlexandru Dutu
This patch sets the CPU status to idle when the last active thread gets suspended.
2015-02-05config: rename 'file' varSteve Reinhardt
Rename uses of 'file' as a local variable to avoid conflict with the built-in type of the same name.
2015-02-05config: make M5_PATH a real search pathSteve Reinhardt
Although you can put a list of colon-separated directory names in M5_PATH, the current code just takes the first one that exists and assumes all files must live there. This change makes the code search the specified list of directories for each individual binary or disk image that's requested. The main motivation is that the x86/Alpha binaries and the ARM binaries are in separate downloads, and thus naturally end up in separate directories. With this change, you can have M5_PATH point to those two directories, then run any FS regression test without changing M5_PATH. Currently, you either have to merge the two download directories or change M5_PATH (or do something else I haven't figured out).
2015-02-03mem: Clarify express snoop behaviourAndreas Hansson
This patch adds a bit of documentation with insights around how express snoops really work.
2015-02-03mem: Clarify cache behaviour for pending dirty responsesAndreas Hansson
This patch adds a bit of clarification around the assumptions made in the cache when packets are sent out, and dirty responses are pending. As part of the change, the marking of an MSHR as in service is simplified slightly, and comments are added to explain what assumptions are made.
2015-02-03base: add an accessor and operators ==,!= to address rangesCurtis Dunham
2015-02-03config: Add XOR hashing to the DRAM channel interleavingAndreas Hansson
This patch uses the recently added XOR hashing capabilities for the DRAM channel interleaving. This avoids channel biasing due to strided access patterns.
2015-02-03base: Add XOR-based hashed address interleavingAndreas Hansson
This patch extends the current address interleaving with basic hashing support. Instead of directly comparing a number of address bits with a matching value, it is now possible to use two independent set of address bits XOR'ed together. This avoids issues where strided address patterns are heavily biased to a subset of the interleaved ranges.
2015-02-03config: Adjust DRAM channel interleaving defaultsAndreas Hansson
This patch changes the DRAM channel interleaving default behaviour to be more representative. The default address mapping (RoRaBaCoCh) moves the channel bits towards the least significant bits, and uses 128 byte as the default channel interleaving granularity. These defaults can be overridden if desired, but should serve as a sensible starting point for most use-cases.
2015-02-03style: Update the style checker to handle new include orderAndreas Sandberg
As of August 2014, the gem5 style guide mandates that a source file's primary header is included first in that source file. This helps to ensure that the header file does not depend on include file ordering and avoids surprises down the road when someone tries to reuse code. In the new order, include files are grouped into the following blocks: * Primary header file (e.g., foo.hh for foo.cc) * Python headers * C system/stdlib includes * C++ stdlib includes * Include files in the gem5 source tree Just like before, include files within a block are required to be sorted in alphabetical order. This changeset updates the style checker to enforce the new order.
2015-02-03sim: Remove test for non-NULL this in EventAndreas Sandberg
The method Event::initialized() tests if this != NULL as a part of the expression that tests if an event is initialized. The only case when this check could be false is if the method is called on a null pointer, which is illegal and leads to undefined behavior (such as eating your pets) according to the C++ standard. Because of this, modern compilers (specifically, recent versions of clang) warn about this which we treat as an error. This changeset removes the redundant check to fix said warning.
2015-02-03dev: Correctly clear interrupts in VirtIO PCIAndreas Sandberg
Correctly clear the PCI interrupt belonging to a VirtIO device when the ISR register is read.