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AgeCommit message (Expand)Author
2014-04-23sim: Use correct unit for abort messageAndreas Hansson
2014-04-23cpu: Fix setTranslateLatency() bug for squashed instructionsMitchell Hayenga
2014-04-23misc: Proper type check and import for PortRefSascha Bischoff
2014-04-01cpu: Fix case where o3 lsq could print out uninitialized dataMitch Hayenga
2014-04-01mem: Don't print out the data of a cache blockMitch Hayenga
2014-04-23arm: Don't use a stack allocated mnemonicMitchell Hayenga
2014-04-23cpu: Add O3 CPU width checksDam Sunwoo
2014-04-23base: explicitly suggest potential use of 'All' debug flagsCurtis Dunham
2014-04-23arch: remove 'null update' check in isa-parserCurtis Dunham
2014-02-10stats: better error message for uninitialized statisticCurtis Dunham
2014-04-22stats: updates for pc-switcheroo-full due to o3 smt fixAndreas Hansson
2014-04-19stats: updates due to o3 smt fixNilay Vaish
2014-04-19ruby: slicc: remove old documentationNilay Vaish
2014-04-19ruby: slicc: slight change to rule for transitionsNilay Vaish
2014-04-19o3: Fix occupancy checks for SMTFaissal Sleiman
2014-04-19ruby: recorder: Fix (de-)serializing with different cache block-sizesMarco Elver
2014-04-19config: ruby: remove memory controller from network testNilay Vaish
2014-04-14arm: set default kernels for VExpress_EMM and VExpress_EMM64Anthony Gutierrez
2014-04-13scons: Fix python-config parsing by adding strip()Andreas Hansson
2014-04-10config: add num-work-ids command line optionGedare Bloom
2014-04-10scons: compile on systems where python2 and python3 co-existStian Hvatum
2014-04-09kvm, x86: Add initial support for multicore simulationAndreas Sandberg
2014-04-09dev: Protect PollEvent processing when running in parallel modeAndreas Sandberg
2014-04-08ruby: slicc: change enqueue statementNilay Vaish
2014-04-08ruby: coherence protocols: drop the phrase IntraChipNilay Vaish
2014-04-03sim: Add the ability to lock and migrate between event queuesAndreas Sandberg
2014-04-01ext: add McPAT sourceAnthony Gutierrez
2014-04-01arm: fix typos in makefile for ARM m5 util and link staticallyAnthony Gutierrez
2014-04-01configs: use SimpleMemory when using ruby in se modeNilay Vaish
2014-03-25cpu: o3: lsq: Fix TSO implementationMarco Elver
2014-03-23stats: Update stats for DRAM changesAndreas Hansson
2014-03-23mem: Track DRAM read/write switching and add hysteresisAndreas Hansson
2014-03-23mem: Rename SimpleDRAM to a more suitable DRAMCtrlAndreas Hansson
2014-03-23mem: Change memory defaults to be more representativeAndreas Hansson
2014-03-23mem: Add close adaptive paging policy to DRAM controller modelWendy Elsasser
2014-03-23mem: DRAM controller tidying upAndreas Hansson
2014-03-23mem: Fix bug in DRAM bytes per activateAndreas Hansson
2014-03-23mem: Limit the accesses to a page before forcing a prechargeAndreas Hansson
2014-03-23mem: Make DRAM write queue draining more aggressiveAndreas Hansson
2014-03-23config: Add a DRAM efficiency-sweep scriptAndreas Hansson
2014-03-23cpu: DRAM Traffic GeneratorNeha Agarwal
2014-03-23mem: DDR3 config for comparing with DRAMSim2Neha Agarwal
2014-03-23mem: More descriptive address-mapping scheme namesAndreas Hansson
2014-03-23scons: Shush sconsCurtis Dunham
2014-03-23misc: Fix -q (quiet) flagStan Czerniawski
2014-03-23ruby: Move Ruby debug flags to ruby dir and remove stale optionsAndreas Hansson
2014-03-23util: Add support for detection of gzipped packet tracesAndreas Hansson
2014-03-23mem: Include the DRAMSim2 wrapper in NULL buildAndreas Hansson
2014-03-23ext: Fix typo in DRAMSim2 SConscriptAndreas Hansson
2014-03-23mem: CommMonitor trace warn on non-timing modeSascha Bischoff