summaryrefslogtreecommitdiff
AgeCommit message (Expand)Author
2014-10-16sim: Add typedefs for PMU probe pointsAndreas Sandberg
2014-10-16sim: Add support for serializing BitUnionXXAndreas Sandberg
2014-10-16config: Add the ability to read a config file using C++ and PythonAndreas Hansson
2014-10-16scons: Add Undefined Behavior Sanitizer (UBSan) optionAndreas Hansson
2014-09-22scons: Add --without-tcmalloc build optionCurtis Dunham
2014-08-12scons: Generate a single debug flag C++ fileCurtis Dunham
2014-10-16scons: create dummy target to have SWIG generate C++ classesCurtis Dunham
2014-10-16config: Add a --without-python option to build processAndrew Bardsley
2014-10-16stats: Small bump of trailing statsAndreas Hansson
2014-10-11stats: updates due to changes to x86, stale configs.Nilay Vaish
2014-10-11cpu: Fix o3 SMT IQCount bugAndrew Lukefahr
2014-10-11util: adds a script for using DSENTNilay Vaish
2014-10-11ext: dsent: adds a Python interface, drops C++ oneNilay Vaish
2014-10-11ext: add the source code for DSENTNilay Vaish
2014-10-11ruby: network: garnet: add statistics for different activitiesNilay Vaish
2014-10-11ruby: network: garnet: remove functions for computing powerNilay Vaish
2014-10-11ruby: drop Orion network power modelNilay Vaish
2014-10-11ruby: mesi: slight renamingNilay Vaish
2014-10-11config: separate function for instantiating a memory controllerNilay Vaish
2014-10-11ruby: structures: coorect #ifndef macros in header filesNilay Vaish
2014-10-11ruby: moesi hammer: correct typo in master-slave assignmentNilay Vaish
2014-06-13x86: add LongModeAddressSize function to cpuidJiuyue Ma
2014-07-17config, x86: Ensure that PCI devs get bridged to the memory busJiuyue Ma
2014-07-17config, x86: swap bus_id of ISA/PCI in X86 IntelMPTableJiuyue Ma
2014-10-11sim: draining bug for fast-forwaring multiple coresAndrew Lukefahr
2014-10-11base: addr range: slight change to validity checkNilay Vaish
2014-10-11base: misc: Add missing header file.Nilay Vaish
2014-10-09stats: Add DRAM power statistics to reference outputAndreas Hansson
2014-07-29mem: DRAMPower integration for on-line DRAM power statsOmar Naji
2014-07-29mem: Add DRAMPower wrapping classOmar Naji
2014-07-25mem: Add missig timing and current parameters to DRAM configsOmar Naji
2014-10-09mem: Remove DRAMSim2 DDR3 configurationOmar Naji
2014-10-09ext: Add DRAMPower to enable on-line DRAM power modellingAndreas Hansson
2014-10-09config: Add Current as a parameter typeAndreas Hansson
2014-10-09cpu: Remove Ozone CPU from the source treeMitch Hayenga
2014-10-09scons: Warn for known gcc and swig incompatibilitiesAndreas Hansson
2014-10-09mem: Add packet sanity checks to cache and MSHRsAndreas Hansson
2014-10-09mem: Allow packet queue to move next send event forwardAndreas Hansson
2014-10-01misc: Fix issues identified by static analysisAndreas Hansson
2014-10-01arm: Use MiscRegIndex rather than int when flatteningAndreas Hansson
2014-10-01arm: More UBSan cleanups after additional full-system runsAndreas Hansson
2014-09-28stats: Update stats to reflect ARM fixesAndreas Hansson
2014-09-27arm: Fixed undefined behaviours identified by gccAndreas Hansson
2014-09-27arch: Use const StaticInstPtr references where possibleAndreas Hansson
2014-09-27scons: Address issues related to gcc 4.9.1Andreas Hansson
2014-09-27dev: Output invalid access size in IsaFake panicCurtis Dunham
2014-09-27mem: Output precise range when XBar has conflictsCurtis Dunham
2014-09-27mem: Provide better diagnostic for unconnected portCurtis Dunham
2014-09-27misc: Fix a bunch of minor issues identified by static analysisAndreas Hansson
2014-09-21stats: update t1000 stats for recent changesSteve Reinhardt
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 21:59:45 +0000