summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2017-05-30misc: Reorder sources in util/tlm and rewrite build scriptsChristian Menard
* Use one SConstruct to build everything instead of one SConstruct for each example. * Introduce SConscripts for sub-directories. * Build in 'build' instead of the source tree. * Build and link to SystemC from the ext/systemc directory. This ensures that SystemC does not need to be installed on the host and avoids possible issues caused by an incompatible SystemC build. * Update the README and add some minor fixes Change-Id: I641ed94f542626864fb7af499ad1be8fd4ad929f Reviewed-on: https://gem5-review.googlesource.com/3480 Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-29ext: Revamp the systemc SConscripts.Gabe Black
The existing scripts were including pthread code and QT code at the same time, and also insisting on an having a set of architecture specific source files for whatever the current architecture is. This change selects using either QT or pthreads based on the host architecture, distributes accumulating source files, list source files explicitly (to avoid including redundant coroutine libraries) and makes scons insist on an architecture specific QT implementation only if QT is being used. It also defines a preprocessor symbol which tells some headers whether or not pthreads are being used, and also clones the scons environment to avoid leaking flags into the main environment used to compile gem5 itself. If the host architecture isn't supported by systemc, a warning will be printed, and the various build products and SConscript files will be skipped over. Change-Id: I1a40123a11e49e02922a054f093246cf197087bf Reviewed-on: https://gem5-review.googlesource.com/3461 Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Reviewed-by: Christian Menard <christian.menard@tu-dresden.de> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-26x86: Rework how VEX prefixes are decoded.Gabe Black
Remove redundant information from the ExtMachInst, hash the vex information to ensure the decode cache works properly, print the vex info when printing an ExtMachInst, consider the vex info when comparing two ExtMachInsts, fold the info from the vex prefixes into existing settings, remove redundant decode code, handle vex prefixes one byte at a time and don't bother building up the entire prefix, and let instructions that care about vex use it in their implementation, instead of developing an entire parallel decode tree. This also eliminates the error prone vex immediate decode table which was incomplete and would result in an out of bounds access for incorrectly encoded instructions or when the CPU was mispeculating, as it was (as far as I can tell) redundant with the tables that already existed for two and three byte opcodes. There were differences, but I think those may have been mistakes based on the documentation I found. Also, in 32 bit mode, the VEX prefixes might actually be LDS or LES instructions which are still legal in that mode. A valid VEX prefix would look like an LDS/LES with an otherwise invalid modrm encoding, so use that as a signal to abort processing the VEX and turn the instruction into an LES/LDS as appropriate. Change-Id: Icb367eaaa35590692df1c98862f315da4c139f5c Reviewed-on: https://gem5-review.googlesource.com/3501 Reviewed-by: Joe Gross <joe.gross@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2017-05-25x86: sim: Make 32 bit x86 processes work again.Gabe Black
When the LiveProcess class was renamed to be just Process, the CL author also changed the syscall function from a virtual function into a regular one. Unfortunately, the I386Process class overrode the syscall function to adjust the return address so that control would return to the right place. Without that adjustment, 32 bit x86 process would segfault and die immediately after their first system call. This change reinstates the virtual specifier on the base syscall function, and adds an override keyword on the I386Process's version so that it won't be orphaned again in the future. It also fixes some small style issues the style checker script complained about. Change-Id: I0d1178ea0eda6676050c8fc043820a2bb4d99c0d Reviewed-on: https://gem5-review.googlesource.com/3500 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-24util: generate fully qualified paths for cscopeGedare Bloom
Change-Id: I318c185b117b9608110544526fbaaa3fdcdeb8bc Signed-off-by: Gedare Bloom <gedare@rtems.org> Reviewed-on: https://gem5-review.googlesource.com/3260 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-24arm: Fix incorrect handling of PMEVTYPERx_EL0 in PMUAndreas Sandberg
The PMU model currently doesn't calculate the PMU event counter index correctly for writes to the PMEVTYPER[0-5]_EL0 registers. Fix this obvious mistake. Change-Id: I2913eedddeb98480660e2d63948f6d727adf5ab8 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3121 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
2017-05-24python: Fix PyEvent reference counting bugAndreas Sandberg
The current implementation of reference counting for PyEvents only partially works. The native object is currently kept alive while it is in the event queue. However, if the Python object goes out of scope, the Python side of this object is garbage collected which leaves a "dangling" native object. This results in confusing error messages where PyBind is unable to find the Python implementation of an event when it is triggered. Implement reference counting using the generalized reference counting API instead. Change-Id: I4e8e04abc4f61dff238d718065f5371e73b38ab3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3222 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-24sim: Add hooks to implement event reference countingAndreas Sandberg
We currently only support deleting an event if it is triggered and not re-scheduled. This is fine for most native code. However, there are cases where Python needs to count references to make sure that the Python object stays live while the native object is live. Generalise the mechanism used to implement by adding reference counting hooks to the event base class: * Event::acquire() / Event::acquireImpl() * Event::release() / Event::releaseImpl() These calls can be used to implement both reference counting and the existing AutoDelete functionality. The default implementation in Event maintains backwards compatibility with the existing AutoDelete feature by ignoring acquireImpl() and deleting the event on releaseImpl() if it isn't scheduled anymore. Since AutoDelete functionality is no longer the only way events can be managed, this change introduces the new Managed flag. This flag activates automatic memory management. The acquireImpl()/releaseImpl() methods are only called from acquire()/release() it is set. To maintain backwards compatibility, AutoDelete is used as an alias for Managed. Change-Id: I5637984c906a9d44c22780712cf1c521b8297149 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3221 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-23arch-riscv: Fix bad stack initializationAlec Roelke
This patch fixes a problem with RISC-V initial stack setup in SE mode where the AT_RANDOM aux vector value contains an address that is too close to the top of the stack and doesn't fit the required 16 bytes. To fix this, the program header table was added to the top of the stack just like the RISC-V proxy kernel does. Change-Id: I814562e060ff041cd0d7a7c54c3685645bd325a3 Reviewed-on: https://gem5-review.googlesource.com/3401 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-05-23arch-arm: Fix some poorly done type max and min in NEONRekai Gonzalez-Alberquilla
The ISA code for ARM calculates min and max elements for types using bit manipulation. That triggers some warnings, treated as errors, as the compiler can tell that there is an overflow and the sign flips. Fixed using standard lib definitions instead. Change-Id: Ie2331b410c7f76d4bd87da5afe9edf20c8ac91b3 Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3481 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-22ext: Upgrade PyBind11 to version 2.1.1Andreas Sandberg
Change-Id: I16870dec402d661295f9d013dc23e362b2b2c169 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3225 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-22python: Prevent Python wrappers from deleting SimObjectsAndreas Sandberg
The PyBind wrappers could potentially delete SimObjects if they don't have any references. This is not desirable since there could be pointers to such objects within the C++ world. This problem doesn't normally occur since Python typically holds a pointer to the root node as long as the simulator is running. Prevent SimObject and Param deletion by using a PyBind-prescribed unique_ptr with a dummy deleter as the pointer wrapper for the Python world. Change-Id: Ied14602c9ee69a083a69c5dae1b5fcf8efb4548a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3224 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-05-22python: Fix weird memory issue in wrapped AddrRange vectorsAndreas Sandberg
There is a weird issue with the PyBind wrapper of vector<AddrRange>. Assigning new values to a param that is a vector of AddrRange sometimes results in an out-of-bounds memory access. We work around this issue by treating AddrRange vectors as opaque types. This slightly changes the semantics of the wrapper since Python now manipulates the real object rather than a copy that has been converted to a list. Change-Id: Ie027c06e7a7262214b43b19a76b24fe4b20426c5 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Timothy Hayes <timothy.hayes@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3223 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-22scons: Enable explicitly building something with no variant.Gabe Black
The SConstruct currently expects all explicit targets to be under a variant directory like ARM or X86 which tells it what settings to use, etc. There are things which scons knows how to build however, which do not live under a variant directory, specifically everything under ext. This change makes scons not look for a variant directory when it encounters a target which is built by something in ext. This enables things like explicitly building the systemc libraries, for example. Change-Id: I8982a96fe49e3cb970ec78e11cea08703990c686 Reviewed-on: https://gem5-review.googlesource.com/3460 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Christian Menard <christian.menard@tu-dresden.de> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-19python: Remove unused readline importAndreas Sandberg
The readline module is imported by main.py but doesn't seem to be used. Change-Id: I7888e3b6ad0a0fedc14b0feec2adf0a39883bbf8 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3421 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-19base, sim, arch: Fix clang 5.0 warningsAndreas Sandberg
Compiling gem5 with recent version of clang (4 and 5) triggers warnings that are treated as errors: * Global templatized static functions result in a warning if they are not used. These should either be declared as static inline or without the static identifier to avoid the warning. * Some templatized classes contain static variables. The instantiated versions of these variables / templates need to be explicitly declared to avoid a compiler warning. Change-Id: Ie8261144836e94ebab7ea04ccccb90927672c257 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3420 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-18base: Refactor the GDB code.Gabe Black
The new version modularizes the implementation of the various commands, gets rid of dynamic allocation of the register cache, fixes some small style problems, and uses exceptions to simplify error handling internal to the GDB stub. Change-Id: Iff3548373ce4adfb99106a810f5713b769df89b2 Reviewed-on: https://gem5-review.googlesource.com/3280 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Boris Shingarov <shingarov@gmail.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-18syscall_emul, riscv: add override keyword to RISCV Process classBrandon Potter
Change-Id: I2a146ae57aac3787389997961208474a97e7c155 Reviewed-on: https://gem5-review.googlesource.com/3360 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-05-18configs: fix cpu names in big.LITTLE examplePierre-Yves Péneau
CPU aliases have been dropped, this change fixes the big.LITTLE example. Change-Id: Idd59a6eca93448ef0e23087365fb5452bcef9247 Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/3300 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-18arm, config: added support for ex5 model of big.LITTLEPierre-Yves Péneau
This patch enables using calibrated big and LITTLE cores, ex5_big and ex5_LITTLE instead of the default 'arm_detailed' and 'minor' cpus. The ex5 model is based on the Samsung Exynos 5 Octa (5422) SoC. Operation and memory hierarchy latencies have been calibrated using the lmbench micro-benchmark suite. The preliminary validation results have been published as: 'Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration', in International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC'16), Lyon, France (Sep, 2016). From http://reviews.gem5.org/r/3666 Change-Id: I4935dee0a9222bd1bf7adfccb9443014945bb2d7 Signed-off-by: Anastasiia Butko <abutko@lbl.gov> Signed-off-by: Pierre-Yves Péneau <pierre-yves.peneau@lirmm.fr> Reviewed-on: https://gem5-review.googlesource.com/2464 Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-18ext: Include SystemC 2.3.1 into gem5Matthias Jung
In the past it happened several times that some changes in gem5 broke the SystemC coupling. Recently Accelera has changed the licence for SystemC from their own licence to Apache2.0, which is compatible with gem5. However, SystemC usually relies on the Boost library, but I was able to exchange the boost calls by c++11 alternatives. The recent SystemC version is placed into /ext and is integrated into gem5's build system. The goal is to integrate some SystemC tests for the CI in some following patches. Change-Id: I4b66ec806b5e3cffc1d7c85d3735ff4fa5b31fd0 Reviewed-on: https://gem5-review.googlesource.com/2240 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-17config: Changes to boot Android NWeiping Liao
necessary kernel command line options in FSConfig.py Change-Id: Id66f640b6beb4efa9c23080c3d2516eda688c72d Reviewed-on: https://gem5-review.googlesource.com/3320 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-16x86: Fix the multiplication microops.Gabe Black
If the operands were 64 bit, an intermediate calculation could lose a carry bit. This change rearranges that intermediate calculation if the operand width is large, and reworks the microop implementation in general in an attempt to make it easier to understand. Change-Id: Ib36333f3f2695a33cd9623e43682de22ebd2e7ea Reviewed-on: https://gem5-review.googlesource.com/3381 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2017-05-16python: Add a helper function to create Python eventsAndreas Sandberg
Add a helper function, m5.event.create(), to create events from Python. This function takes a callable Python object (e.g., a function) as an argument and optionally a priority as a keyword argument. This function was accidentally dropped from the public API when switching to PyBind. Change-Id: Icbd0e392d9506934ec2c9f541199aa35c1c2df8c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3220 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-05-15style: fix line lengths and include orderingBrandon Potter
The style checker complains about line length and ordering for these files. This fix should make these two files kosher. Change-Id: I822a0518a98d9e379a543d2017e90c4e9666a58d Reviewed-on: https://gem5-review.googlesource.com/3380 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2017-05-15cpu: fix problem with forwarding and locked loadAlec Roelke
If a (regular) store is followed closely enough by a locked load that overlaps, the LSQ will forward the store's data to the locked load and never tell the cache about the locked load. As a result, the cache will not lock the address and all future store-conditional requests on that address will fail. This patch fixes that by preventing forwarding if the memory request is a locked load and adding another case to the LSQ forwarding logic that delays the locked load request if a store in the LSQ contains all or part of the data that is requested. [Merge second and last if blocks because their bodies are the same.] Change-Id: I895cc2b9570035267bdf6ae3fdc8a09049969841 Reviewed-on: https://gem5-review.googlesource.com/2400 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-15arm, dev: stub out GIC distributor interrupt groupsCurtis Dunham
We don't implement the GICD_IGROUPRn registers, which is allowed, but to be correct, they should be RAZ/WI (read as zero, writes ignored). Change-Id: I8039baf72f45c0095f41e165b8e327c79b1ac082 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2620 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-12base: Make the VNC server more resilient.Gabe Black
If the client does something bad, don't kill the whole simulation, just complain, drop the client and keep going. Change-Id: I824f2d121e2fe03cdf4323a25c192b68e0370acc Reviewed-on: https://gem5-review.googlesource.com/3200 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-12misc: Make the remote GDB stub more resilient to bad connections.Gabe Black
Currently, if the remote gdb stub fails to read a byte from an incoming packet because the connection has been dropped, the read call will return anyway and the calling code will have no way to know something bad happened. It might reattempt the read over and over again waiting for some particular byte, doomed to never make forward progress. This change modifies the remote GDB code so that if a read or write call fails, it will instead detach from the debugger and continue. Before this change, When simulating a port scan, ie connecting to the debugger port and then immediately dropping the connection using this command: nc -v -n -z -w 1 127.0.0.1 7000 gem5 would enter the previously described death spiral. After it, gem5 detaches from the bad connection and resumes execution. Subsequently attaching with gdb was successful. This code is written in a C centric style, and would benefit from some refactoring. Change-Id: Ie3c0bb35b9cfe3671d0f731e3907548bae0d292f Reviewed-on: https://gem5-review.googlesource.com/3180 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-12syscall_emul: Fix undefined macro behaviorAndreas Sandberg
Clang's UBSAN implementation complains about macros that expand to expressions that contain 'defined'. Explicitly set the various feature macros to 1 or 0 to avoid this issue. Change-Id: Iba239dacfe526c43ab9c5da5183a350fc4fdc57d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3241
2017-05-12arm: Remove unused DumpStatsPCEventF class in FreeBSD systemAndreas Sandberg
The DumpStatsPCEventF is declared but lacks an implementation. This confuses RTTI in clang. Remove this class since it is clearly not needed. Change-Id: Ib95f09f2ba8593f8d0e072b96afd5f8a9ed31070 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3240 Reviewed-by: B.A. Zeeb <baz21@cam.ac.uk>
2017-05-10scons: Use the generalized switching headers on the GPU ISA.Gabe Black
Now that the switching header implementation has been generalized, there's no need to have two nearly identical implementations for the two different groups of headers. Change-Id: Ie7c24fcddbc672ac5ca2d69bfc35696f42c55580 Reviewed-on: https://gem5-review.googlesource.com/2984 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-10scons: arch: Generalize the switching header code.Gabe Black
Factor out the ISA ness of the switching header generating function. Also turn it into a SCons builder which builds a single header, and a wrapping method which uses the builder on a group of header files which all target the same subdirectory. Change-Id: I87705f97b6ebd9baebd4ebcfea19cc1218a64ad0 Reviewed-on: https://gem5-review.googlesource.com/2983 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-09config: Fix up some configs to not use CPU aliases.Gabe Black
Support for CPU aliases were removed recently. Change-Id: I3c1173dc34170d8639d95e52bf660f248848f77f Reviewed-on: https://gem5-review.googlesource.com/3100 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-05-09scons: Get rid of the all_isa_deps variable.Gabe Black
This value can be computed more directly and more locally near where it's used. Change-Id: Ib5f45015494a6c8033ce0ac4b8931688f37492c8 Reviewed-on: https://gem5-review.googlesource.com/2982 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-09misc: Add the --listener-loopback-only command line option.Gabe Black
This option invokes the Listener::loopbackOnly() static function which will make the port listeners bind to the loopback device exclusively and ignore connections on other devices. That prevents external agents like port scanners from disrupting simulations with spurious connections. Change-Id: I46b22165046792a6f970826c109bdbce7db25c84 Reviewed-on: https://gem5-review.googlesource.com/3082 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-09misc: Expose the listener loopbackOnly function to python.Gabe Black
Change-Id: Ibb405af54a46a93706a6f476b5314491e84be0c8 Reviewed-on: https://gem5-review.googlesource.com/3081 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-09base: Teach the socket listeners how to bind to the loopback.Gabe Black
The loopback device will allow access to various services like remote GDB debugging, connecting to the terminal, etc., without letting external agents like port scanners connect and disrupting the simulation. Change-Id: I76dccbf152fa278ae9f342b25f7e345a1329fbe4 Reviewed-on: https://gem5-review.googlesource.com/3080 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-09style: Treat PyBind headers as Python headersAndreas Sandberg
Some PyBind11 headers need to include Python.h. This means that we need to include PyBind11 headers before any standard library headers. Enforce this by applying the Python.hh rules for anything in pybind11/. Change-Id: Id175a4f613960a17f84f98b81bfd02806e905d5a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3120 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
2017-05-09python: Fix debug flag listing regressionAndreas Sandberg
The PyBind11 changes slightly modified gem5's internal debug interfaces. The corresponding change to the public API went missing before the new bindings were merged. This change updates the Python glue to use the new interface. Change-Id: I3ecca5a3f6c35b99d55126d697371124f81a12dd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3140 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-09util, arm: Support mmapped m5ops on aarch64Andreas Sandberg
Add support for memory-mapped m5ops in the aarch64 version of the m5 utility. To enable support for memory-mapped m5ops, compile the tool with the define M5OP_ADDR set to the base of the m5op PA range. Change-Id: I13e21e48536b9849bf4081411b66b2f350f7a8ac Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2966
2017-05-09arm: Enable m5ops by default for VExpress_GEM5_V1Andreas Sandberg
Allocate 0x10010000-0x1001ffff for m5 pseudo-ops. This range is a part of the CS5 address range in the RS1/RS2 memory map. Change-Id: Ica45cd53bc4ebb62966afa099fa465e27fb0452c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2965
2017-05-09arm: Add support for memory-mapped m5opsAndreas Sandberg
Add support for a memory mapped m5op interface. When enabled, the TLB intercepts accesses in the 64KiB region designated by the ArmTLB.m5ops_base parameter. An access to this range maps to a specific m5op call. The upper 8 bits of the offset into the range denote the m5op function to call and the lower 8 bits denote the subfunction. Change-Id: I55fd8ac1afef4c3cc423b973870c9fe600a843a2 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2964
2017-05-09kvm, arm: Fix incorrect PSTATE syncAndreas Sandberg
The state transfer code wasn't reading back PSTATE correctly from the CPU prior to updating the thread context and was incorreclty writing the register as a 32-bit value when updating KVM. Correctly read back the state before updating gem5's view of PSTATE and cast the value to a uint64_t. Change-Id: I0a6ff5b77b897c756b20a20f65c420f42386360f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2963 Reviewed-by: Rahul Thakur <rjthakur@google.com>
2017-05-09util: Correctly handle short writes in m5 (read|exec)fileAndreas Sandberg
The m5 tool has subcommands that writes a file to the simulated file system. The implementation of this command currently doesn't check the return value from write, which leads to compiler warnings and potentially incorrect behavior. Add the necessary checks. Change-Id: If558534d3245aa24cf15edf06bd0af4c6ba3908c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2962 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2017-05-09util: Add the m5_loadsymbol pseudo op to the m5 toolAndreas Sandberg
Change-Id: Ib8bf4eac77170db8b2bf44796fd9d46b02217d03 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3122 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com>
2017-05-09util: Fix incorrect use of m5_loadsymbolAndreas Sandberg
It seems like the m5 utility incorrectly called m5_loadsymbol instead of m5_addsymbol. Judging by the signature of the loadsymbol command, the expected behavior is to add a new symbol to gem5's symbol table. This is behavior is implemented by m5_addsymbol. Change-Id: I83b61c48d6f8d7b1e8b57d884dfca00481c83c3a Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2961 Reviewed-by: Gabe Black <gabeblack@google.com>
2017-05-09misc: fix build failure in cxx_config examplePaul Rosenfeld
Fix a missing header in the cxx_config example which is used as a simple example of using libgem5.so without python. Change-Id: I758bfe42ba735ce0c7eaedd49b94a130e3bd21e3 Reviewed-on: https://gem5-review.googlesource.com/3000 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2017-05-08scons: Get rid of the PHONY_BASE construction variable.Gabe Black
The value of that variable can be computed more directly and more locally to where it's consumed. Change-Id: I5ca1f732a34e22d4dae2aeb6ee7fc8adebe1caa0 Reviewed-on: https://gem5-review.googlesource.com/2981 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-05-08util: Fix incorrect return type in m5 writefileAndreas Sandberg
Change-Id: Ic24a1c3c1488e970ed27bb6b99262d201f535384 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2960 Reviewed-by: Gabe Black <gabeblack@google.com>