Age | Commit message (Collapse) | Author |
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arch/alpha/ev5.cc:
actually implement the cycle count register
arch/alpha/isa_desc:
the rpcc instruction really just reads the cycle count
register
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extra : convert_revision : a0edec85672377a62b90950efc17b62b375220b1
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arch/alpha/ev5.cc:
Handle writing IPR_CC and IPR_CC_CTL slightly more intelligently.
(Very slightly).
arch/alpha/isa_desc:
Upper half of rpcc result comes from value written
to IPR_CC, not actual cycle counter.
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extra : convert_revision : 7161989db8a3f040d0558e2e5a1a162ed1cb4125
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arch/alpha/isa_desc:
Add copy_load and copy_store insts (ldf and stf respectively)
cpu/simple_cpu/simple_cpu.hh:
Add copy functions to SimpleCPU as well
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extra : convert_revision : 1fa041da582b418c47d4eefc22dabba978a50e2d
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arch/alpha/osfpal.cc:
Add a string for copypal.
arch/alpha/osfpal.hh:
Add a code for copypal.
cpu/static_inst.hh:
Add an IsCopy flag.
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extra : convert_revision : 19e3d90368454806029ad492eace19cd0924fe9f
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extra : convert_revision : 67a9e36cda69da6b462e6a30d6daa047ce48fdde
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the request locally until it is retransmitted.
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extra : convert_revision : cc89d6c4b7f21b7252c172c694633ce1daae30eb
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extra : convert_revision : e83f6895bceb0ced656e90275ec1a93d0af5498d
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it actually do something on FullCPU. Still disabled, as it
causes detailed-boot to hang when you turn it on.
arch/alpha/isa_desc:
Add EAComp and MemAcc pseudo-instructions to prefetch StaticInst.
cpu/simple_cpu/simple_cpu.hh:
Changed prefetch() return type from Fault to void.
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extra : convert_revision : c7cb42682bfea6af117c87d4dfdb06176b6fe6b7
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won't accidentally be issued to the memory system.
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extra : convert_revision : 5696a09abcdee54c8bec72d9374f7944fb136740
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extra : convert_revision : 6ae9b4af78cff3c8e5dc367fdbefad496a28857d
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sampling cpu also.
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extra : convert_revision : d3947c55f95bb03e73a815188a517043f39925d4
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extra : convert_revision : 4f08f8c7ab380436b2ad2c30ba53d9fe305e4496
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into ziff.eecs.umich.edu:/z/binkertn/research/m5/latest
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extra : convert_revision : 2a258d16ba51ce34f5748825a94b456abfb577cc
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debug target
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extra : convert_revision : aa16e6256a056e6df9affec6fd973e62e812e23c
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the end of the build process. (Done by doing the registerExecContext() calling sequence in the init() process rather than the create() process).
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
same thing for simple cpu's.
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extra : convert_revision : aac9f91742866fb26f8cace622f9b88454a69662
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util/tracediff:
Quote simulator args so args with spaces get handled correctly.
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extra : convert_revision : b48677bc712be17e6e50ca35680e757ba9364692
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so add some states to indicate that the dma read/write
hasn't issued yet, and add some support to reissue the
request when the interface becomes unblocked.
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extra : convert_revision : 448695a8eb2e9f98554769f3165df1f796adf44a
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physical address
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extra : convert_revision : 9f752d5ab6def492056d4dfe0bda5eecb022ba80
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extra : convert_revision : 786b7fa503436f9a269ebeaedf152c6364874ab5
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extra : convert_revision : 59eaf2c548a88df075b13e78aaa7a4377f20e6c8
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fix serialization
dev/etherlink.cc:
fix serialization
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extra : convert_revision : 6739001f3f97b745d9874bb4c5729cc4909625c2
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sim/sim_object.cc:
serialize objects in the reverse order of their creation.
This causes a SimObject that is dependent on another
to be serialized first. For example, the ethernet device
writes back some data to physical memory while serializing,
so this will cause the physical memory to be serialized
after that, preserving the data written back.
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extra : convert_revision : f9a37b63ce777df1cfecefa80f94f8fc69e42448
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of faking it. Renamed stuff to follow our style. Lots of
general cleanup.
dev/etherpkt.hh:
fix up includes
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extra : convert_revision : fb3a21466cdae00f8747d6e3027c9f2c63569c48
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and member function and will schedule it for the future.
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extra : convert_revision : f5c5a8df0839e1e10716850c2086862c4a5bc499
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make it so that pio devices must respond with some delay.
dev/io_device.cc:
don't forget to include dma_interface.hh so we could use it.
dev/io_device.hh:
the generic BusInterface isn't enough for doing DMA
we need the actual DMAInterface
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extra : convert_revision : 70298d33c8520a3f4ad11aa600825a8cec7e44bf
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cpu/simple_cpu/simple_cpu.cc:
Allow requests to be uncacheable
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extra : convert_revision : 7ab1442f2eec3763d5bc6a6f37b11f663851b12c
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but provide a #define that can be used to put them on
a separate IO bus
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extra : convert_revision : 75d48f312c503ad67d22319db691ef5a0de12996
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extra : convert_revision : 62e8d6b218909c00a97d71e0d3b0f11816499fbf
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base/trace.cc:
base/trace.hh:
take a void * for the raw data
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extra : convert_revision : fc336dc82b4d533c3a0f319977074f26342445ea
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dev/etherdump.cc:
now that init is automatically called by the framework, don't
init twice.
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extra : convert_revision : 16dcdef67aa193ed71ff546e7b255d60f39bf13d
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into ziff.eecs.umich.edu:/z/binkertn/research/m5/memory
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extra : convert_revision : 691c89ebacb3c5a5eb67359ed102646b8547dd17
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extra : convert_revision : b8e4d9c2901c4c784ecca351fd34a3f5a2845473
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and for link events
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extra : convert_revision : 115a9ea8d08bf3e32ecb689962c8a12c9a7dba26
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into ziff.eecs.umich.edu:/z/binkertn/research/m5/memory
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extra : convert_revision : 626baf73d2e26201088b05b4e5fac19292abcb32
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the perl script, the ENV{PWD} does not change.
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extra : convert_revision : e1b2fb3e3b791921b9c3f4bb3b7417ff047bbcbf
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tlb index calls that are called from ExecContext::readIpr
arch/alpha/ev5.cc:
Fix misspeculation bugs for misspeculated IPR accesses
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extra : convert_revision : c9ffcf9ef8123dfcaee1606c05aee8ad60d893d7
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into ziff.eecs.umich.edu:/z/binkertn/research/m5/memory
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extra : convert_revision : 20e6f7edd432952b3c30d4f017058dfd52456fda
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extra : convert_revision : bd0948bc831610f442d5ff6893f0e2a68e3aa83f
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extra : convert_revision : b29c9bbb50994e2567fd58deedb853123d2d69a0
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cpu/memtest/memtest.cc:
Move the trace Addr to the end of the printouts
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extra : convert_revision : 875f0a3f65e07f531a23fea6be07fbf3239ec2c4
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extra : convert_revision : 19800f3879c943addbf4bca747b357a94352b6a8
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extra : convert_revision : 8c071c4f48581a398bebc4f033e18580dca0897f
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physical addresses.
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extra : convert_revision : efb4a5229d88cb3c024e0b24f5916048bd42d589
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extra : convert_revision : 901ef4782d0c9f0d842deba7acdba7896da7e41c
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cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
Add 2 new parameters to control the percentage of unaligned copy sources and destinations.
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extra : convert_revision : 2646ee2f195e9f3e76bc257b8716163ef63a9f40
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into zizzer.eecs.umich.edu:/.automount/ziff/z/binkertn/research/m5/memory
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extra : convert_revision : 99f5289f4143fb09c84694a51b3394d6699d927a
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arch/alpha/vtophys.cc:
fix up vtophys to deal with translations if there
is no ptbr, and to deal with PAL addresses
add ptomem which is just a wrapper for dma_addr
arch/alpha/vtophys.hh:
add ptomem which is a wrapper for dma_addr with the
same usage as vtomem
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extra : convert_revision : 1ae22073d400e87b708a4a7ef501124227fc6c39
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