Age | Commit message (Collapse) | Author |
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m5 style and fixing whitespace. For whitespace, any tabs in
leading whitespace on a line are converted to spaces, and any
trailing whitespace is removed.
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src/arch/sparc/isa/decoder.isa:
Added the extended twin load instructions
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added stuff to implement the extended twin loads. This created alot of duplication which I'll deal with later.
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extra : convert_revision : 5d8bdaacbfe83d21d3a396ce30ace90aeefc54d8
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into zower.eecs.umich.edu:/eecshome/m5/sparcfs
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into zower.eecs.umich.edu:/eecshome/m5/sparcfs
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src/arch/sparc/isa/decoder.isa:
Changed the names of the twin loads to match the 2005 spec. They still use the old format though.
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added code to generate twin loads
src/arch/sparc/isa/formats/mem/util.isa:
Added an alignment check for twin loads
src/arch/sparc/isa/operands.isa:
Comment explaining twin load operands.
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
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extra : convert_revision : a6a40a3bc2e07bc7828de08fa2ce1c847105483d
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
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(but these weren't the cause of the problem).
RangeSize as a function takes a start address, and a SIZE, and will make the range (start, start+size-1) for you.
src/cpu/memtest/memtest.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/lsq.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.hh:
Fix RangeSize arguments
src/dev/alpha/tsunami_cchip.cc:
src/dev/alpha/tsunami_io.cc:
src/dev/alpha/tsunami_pchip.cc:
src/dev/baddev.cc:
pioSize indicates SIZE, not a mask
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extra : convert_revision : d385521fcfe58f8dffc8622260937e668a47a948
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into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
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extra : convert_revision : 92a865a90a7c3e251ed1443f79640f761b359c1d
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we can merge back with newmem.
exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
mmaped_ipr.hh:
fix for build
miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/sparc/miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/mips/mmaped_ipr.hh:
fix for build
src/cpu/exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
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extra : convert_revision : c5b9d56ab99018a91d04de47ba1d5ca7768590bb
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this privilegedString is never used
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extra : convert_revision : 5e6881d467792b670e0009cee8d5e96bc7a79a95
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fix namespace indentations
src/arch/alpha/tlb.cc:
fix namespace indentations
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still use some work.
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fix TICK register reads
reduce the number of readmiscreg accesses,
implement tsb pointer stuff
src/arch/sparc/asi.cc:
flesh out twinx asis
src/arch/sparc/miscregfile.cc:
fix TICK register reads
src/arch/sparc/tlb.cc:
reduce the number of readmiscreg accesses,
implement tsb pointer stuff
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extra : convert_revision : 1995c3b04b7743c6122cbf8ded7c4d5de48fa3c8
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and push those into derived Cache template class to
eliminate a few layers of virtual functions and
conditionals ("if (isCpuSide) { ... }" etc.).
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extra : convert_revision : cb1b88246c95b36aa0cf26d534127d3714ddb774
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into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
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extra : convert_revision : 8cf3e824e4892249b12ed0fd92bb310748b18fa2
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into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
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extra : convert_revision : 82733f9c7bf833cf6bbfbd2aad292f69f52d21bc
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into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
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into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
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extra : convert_revision : 6e58629b1e51f1fc493a89f16c3f2e676dc5d191
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress
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extra : convert_revision : d420ee86454b72b0e5d3a98bac3b496f172c1788
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Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing)
Fix tcc instruction igoner in legion-lock stuff to be correct in all cases
Have console interrupts warn rather than panicing until we figure out what to do with interrupts
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
add a magic miscreg which reads all the bits the tlb needs in one go
src/arch/sparc/tlb.cc:
initialized the context type and id to reasonable values and handle block init stores
src/arch/sparc/tlb_map.hh:
fix bug in tlb map code
src/base/range_map.hh:
fix bug in rangemap code and add range_multimap
(these are probably useful for bus range stuff)
src/cpu/exetrace.cc:
fixup tcc ignore code to be correct
src/dev/sparc/t1000.cc:
make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out
src/unittest/rangemaptest.cc:
fix up the rangemap unit test to catch the missing case
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extra : convert_revision : 70604a8b5d0553aa0b0bd7649f775a0cfa8267a5
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the oldest instruction is passed on to commit).
This fixes a minor bug when multiple FU completions come back out of order (due to the order in which the FUs are freed up), and the oldest redirect isn't recorded properly. The eon benchmark should run now.
src/cpu/o3/iew_impl.hh:
Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit).
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extra : convert_revision : b7d202dee1754539ed814f0fac59adb8c6328ee1
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(read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
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(instead of complaining and exiting).
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there was a fault prior to translation).
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache3
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Runtimes are way too long with current inputs.
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache3
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extra : convert_revision : 7c78ae3298645aed2179ed4f2aa361619406f9de
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into vm1.(none):/home/stever/bk/newmem-cache2
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into zeep.pool:/z/saidi/work/m5.newmem
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Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data
src/arch/sparc/faults.cc:
Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
cleanup/fix page table code
src/arch/sparc/tlb.cc:
implement more mmaped iprs, fix numbered insertion code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.
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extra : convert_revision : d7d771900f6f25219f3dc6a6e51986d342a32e03
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into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
src/arch/sparc/ua2005.cc:
hand merge
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extra : convert_revision : 5157fa5d7053cb93f73241c63871eaae6f58b8a6
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src/arch/sparc/interrupts.hh:
add in thread_context.hh to get access to tc.
get rid of stubs that don't make sense right now.
implement checking and get softint interrupts
src/arch/sparc/miscregfile.cc:
softint should be OR-ed on a write.
src/arch/sparc/miscregfile.hh:
add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs.
src/arch/sparc/ua2005.cc:
implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write.
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extra : convert_revision : d12d1147b508121075ee9be4599693554d4b9eae
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src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
add sparc error asi
src/arch/sparc/faults.cc:
put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
add sparc error register code that just does nothing
fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
fix implementation of HPSTATE write
src/cpu/exetrace.cc:
let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
add l2 error status register fake devices
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Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
Handle access to ASI_QUEUE
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extra : convert_revision : 7a14450485816e6ee3bc8c80b462a13e1edf0ba0
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getting touched.
configs/common/FSConfig.py:
Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
Fix AsiIsNucleus spelling with respect to header file
Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
Flesh out priviledgedString with hypervisor checks
Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
add an IPR traceflag
src/mem/request.hh:
Fix a bad assert() in request
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