Age | Commit message (Collapse) | Author |
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into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
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into zeep.pool:/z/saidi/work/m5.newmem
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into vm1.(none):/home/stever/bk/newmem-head
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extra : convert_revision : c2350e01a052114a264f26551b13fca03a835c61
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Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.
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Caveats:
- Even though memtest is ISA-independent, it will only
run for the Alpha builds, since there's no way to specify
ISA-independent reference files and I didn't want to commit
3 copies since I'm not sure we want to run it for all the
different ISAs anyway.
- Reference outputs were generated on my laptop,
so performance numbers will be low compared to zizzer.
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the middle of one
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fix unaligned accesses in mmaped disk device
src/arch/sparc/isa/decoder.isa:
get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code
src/arch/sparc/isa/formats/basic.isa:
move the cexec into the aexec field
src/cpu/exetrace.cc:
copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer
src/dev/sparc/mm_disk.cc:
src/dev/sparc/mm_disk.hh:
fix unaligned accesses in the memory mapped disk device
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directory where tracediff is.
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definition as well as the declaration.
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in debugging mode (especially valuable for tracediff).
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src/arch/sparc/isa/decoder.isa:
fix rdgsr fault check
src/arch/sparc/tlb.cc:
block asis are now supported
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src/arch/sparc/floatregfile.cc:
fix fp read/writing to registers... looking for suggestions on cleaner ways if anyone has them
src/arch/sparc/isa/decoder.isa:
fix some fp implementations
src/arch/sparc/isa/formats/basic.isa:
add new fp op class that 0 cexec in fsr and sets rounding mode for the up comming op
src/arch/sparc/isa/includes.isa:
include the appropriate header files for the rounding code
src/arch/sparc/miscregfile.cc:
print fsr out when it's read/written and the Sparc traceflgas in on
src/cpu/exetrace.cc:
fix printing of float registers
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extra : convert_revision : 49faab27f2e786a8455f9ca0f3f0132380c9d992
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into zed.eecs.umich.edu:/z/hsul/work/sparc/x86.m5
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into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem
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src/SConscript:
strip doesn't take a src and dest in solaris
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into zeep.pool:/z/saidi/work/m5.newmem
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src/arch/sparc/floatregfile.cc:
Fix serialization for fpreg
src/arch/sparc/intregfile.cc:
fix serialization for intreg
src/arch/sparc/miscregfile.cc:
fix serialization from miscreg
src/arch/sparc/pagetable.cc:
fix serialization for page table
src/arch/sparc/regfile.cc:
need to serialize nnpc
src/arch/sparc/tlb.cc:
write serialization code for tlb
src/cpu/base.cc:
provide a way to find the thread number a context is
serialize the instruction counter
src/cpu/base.hh:
provide a way to find the thread number a context is
and given a thread number find a context pointer
src/cpu/cpuevent.hh:
provide method to get thread context from a cpu event for serialization
src/dev/sparc/t1000.cc:
src/dev/sparc/t1000.hh:
nothing to serialize in t1000
src/sim/serialize.cc:
src/sim/serialize.hh:
Make findObj() work (it hasn't since we did the python conversion stuff)
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-m works as you think it should
Ctrl-C actually ends the simulation now
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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src/arch/sparc/isa/base.isa:
Added passesFpCondition function to help with fbfcc and fbpfcc instructions.
src/arch/sparc/isa/decoder.isa:
Added fbfcc and fbpfcc instructions, and cleaned up branch code slightly.
src/arch/sparc/isa/formats/branch.isa:
Minor cleanup.
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way to do this.
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of the pointer, not the memory.
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setSingleStep
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unimplemented floating point ops.
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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right with respect to quite NaNs, but hopefully we don't need to worry about the distinction.
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into zeep.pool:/z/saidi/work/m5.newmem
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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into zeep.pool:/z/saidi/work/m5.newmem
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