Age | Commit message (Collapse) | Author |
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : fa1e361fcae10fe7a91118007faeeabe3fecba2a
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right now since we don't have cache support for
the atomic instructions.
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extra : convert_revision : b7013e6963885dfe2b4630ac175e24ddad6d42a6
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extra : convert_revision : d068dfec69b28d48fc299a4108e165decfaaace7
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directly configured by python. Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.
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extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
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Fix things so the stats dump happens last.
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extra : convert_revision : ea842dbcbb77dd1c715c4e5b57d2470e558c4265
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into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
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extra : convert_revision : 0959fb162253ff1eed8da0a990f58897322f0e1f
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it's single stepping code.
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extra : convert_revision : 69b1668a850519ab98b02c525ec41ff727eb6036
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arguments.
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extra : convert_revision : dd6b4d14070a2e99c179c5f780c9935847da8eda
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The page table fault should be moved into sim/faults.hh because it's a "fake" m5 fault for se mode and shouldn't vary between architectures.
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extra : convert_revision : cafe25befd64f83a424c1a09f5e62a16df5408ad
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extra : convert_revision : f0a2cdf7d669834b90444fc390b0aceede474737
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what this is for, and it probably doesn't work on anything but Alpha.
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extra : convert_revision : 9bc3833628d31799a7b578c450dac096a19aead3
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Alpha does.
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object?
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from some other include.
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extra : convert_revision : adbd4899508e3d30959a504a48402f01d1187099
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
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extra : convert_revision : b585cea2221377eb2fceea8976c46a17c0034f51
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extra : convert_revision : 099e380395fc1fdaef993b019d3d4e596e8076c2
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src/dev/sparc/iob.cc:
don't warn on cpu restart/idle/halt stuff
tests/SConscript:
add sparc target in test Sconscript
util/regress:
Add SPARC_FS target in regress
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extra : convert_revision : 37fa21700ec4c350d87ca9723bc3359feb81c50a
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into zeep.pool:/z/saidi/work/m5.newmem
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extra : convert_revision : fd6464c9883783c7c2cbefba317f4a0f20dd24cb
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configs/common/FSConfig.py:
add an attachOnChipIO to force people to think about where "onchip" i/o should be connected in their hierarchy
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extra : convert_revision : cf79a9a00760b7daf28063f407a04bd38b956843
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configs/common/FSConfig.py:
Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Add InterruptVector type
src/arch/sparc/interrupts.hh:
rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
Add checkSoftInt to check if a softint needs to be posted
Check that a tickCompare isn't scheduled before scheduling one
Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
update config.ini/out for intrcntrl not having a cpu pointer anymore
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extra : convert_revision : 38614f6b9ffc8f3c93949a94ff04b7d2987168dd
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extra : convert_revision : 9b5ad2704dfd63a1aa8ad0e4275fd0e3a7d32d6d
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nonsensical for x86.
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extra : convert_revision : 2f7845db6d65b353985b474f7012cfbbaece6a39
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non-sensical in x86.
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extra : convert_revision : bba78db3667e214c95bb127872d3fdf546619703
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extra : convert_revision : 438eb74f14e6ea60bab5012110f3946c9213786e
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into iceaxe.int.chaotic.net:/Users/nate/work/m5/outgoing
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extra : convert_revision : b3d48721ead389fa807c0d5392039d4fc71a252e
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extra : convert_revision : 235f85e611a669401c6ddfbdf14244e80eb55888
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-sparc32
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extra : convert_revision : bbd0def502e423e64e2c4f6415a4b043b60c7f90
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