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2006-10-17Fixes to cache eliminating the assumption that the Packet is still valid ↵Ron Dreslinski
after sending out a request. Still need to rework upgrades into this system, but works for now. src/mem/cache/base_cache.cc: Re order code to be more readable src/mem/cache/base_cache.hh: Be sure to delete the copy on a bus block src/mem/cache/cache_impl.hh: Be sure to remove the copy on a writeback success src/mem/cache/miss/mshr_queue.cc: Demorgans to make it easier to understand src/mem/tport.cc: Delete writebacks --HG-- extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
2006-10-17Properly chack the pkt pointer on upgrades to insure no segfaults when ↵Ron Dreslinski
writebacks delete the packet. --HG-- extra : convert_revision : 72b1c6296a16319f4d16c62bc7038365654dbc40
2006-10-17Fix it so that the cache does not assume to gave the packet it sent out via ↵Ron Dreslinski
sendTiming. Still need to fix upgrades to use this path src/mem/cache/base_cache.cc: Copy the pkt to the MSHR before issuing the sendTiming where it may be changed/consumed src/mem/cache/cache_impl.hh: Use copy of packet, because sendTiming may have changed the pkt Also, delete the copy when the time comes --HG-- extra : convert_revision : 635cde6b4f08d010affde310c46b1caf50fbe424
2006-10-17Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : e33d535feb0c3d975dc043efdc86efe0df05800c
2006-10-17Rename 'Machine' to 'SysConfig'.Steve Reinhardt
Clean up a little. --HG-- extra : convert_revision : db5f36776209c76a593205c46b08aa147358f33a
2006-10-17Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : c3650273684f3fbdcd2e14e95d09ee3c6de8d6b6
2006-10-14Get rid of unused CacheBlk << output operator.Steve Reinhardt
--HG-- extra : convert_revision : d5c0aadc35edf5c9495afcd3375f1f64716ef845
2006-10-13Merge 141.212.106.238:/home/gblack/m5/newmem_busGabe Black
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem_bus --HG-- extra : convert_revision : ff15f3805a9ed9aa81e92013d5b57399a30720bb
2006-10-13Fix stats for new bus modelGabe Black
--HG-- extra : convert_revision : c081754c8eb8fa5b8e7336deb3fefb545789b8ac
2006-10-13Fix assertion. I haven't tested it fully (I can't reproduce Lisa's error) ↵Kevin Lim
but I believe it should fix what she's running into (which was definitely a bug). src/cpu/o3/fetch_impl.hh: Move assertion to area where it should really always be true. Sometimes you might recvRetry and not necessarily be blocked (if there was a squash). --HG-- extra : convert_revision : 76ad35357e7f4c44fa544ffed071096a62053018
2006-10-13Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : f62790e46a7e3eb88a6f8c7bfaa08526285248a3
2006-10-13Fix for DMA's in FS caches.Ron Dreslinski
Fix CSHR's for flow control. Fix for Bus Bridges reusing packets (clean flags up) Now both timing/atomic caches with MOESI in UP fail at same point. src/dev/io_device.hh: DMA's should send WriteInvalidates src/mem/bridge.cc: Reusing packet, clean flags in the packet set by bus. src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: Fix CSHR's for flow control. src/mem/packet.hh: Make a writeInvalidateResp, since the DMA expects responses to it's writes --HG-- extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd
2006-10-13fix a bug in CopyStringOut. dprintk appears to work again.Ali Saidi
--HG-- extra : convert_revision : cd0d13a85ddc7599308db8604a8f63a48679cc05
2006-10-12Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem src/cpu/simple/timing.cc: hand merge --HG-- extra : convert_revision : 083bf102249ad9bc63c447dbf85d3863f935f647
2006-10-12replace functional code in tport with fixPacket().Ali Saidi
fixPacket() should be used anywhere a functional packet and timing packet are found to have the same address. --HG-- extra : convert_revision : 783ec438271b24ddb0ae742b4efd1ed7d6be93f3
2006-10-12Merge zizzer:/bk/newmemKorey Sewell
into zooks.eecs.umich.edu:/y/ksewell/research/m5-sim/cleanrepo --HG-- extra : convert_revision : f02fd56fc1ec658fe2a81d0e0b0d053b7606f7f2
2006-10-12config file updatesKorey Sewell
--HG-- extra : convert_revision : b873e0b436d71d86b87b8d9df7115bcc7ceb2b50
2006-10-12Fix CSHR retrysRon Dreslinski
--HG-- extra : convert_revision : caa7664f6c945396fa38ce62fbda018ebed4eaa6
2006-10-12Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem.head --HG-- extra : convert_revision : 0e184a0784100112db5841c587bd3dd638f8bdc0
2006-10-12small bus updates for functional accessesAli Saidi
--HG-- extra : convert_revision : c7a6b199c74ed4b4ffab14bbffb51e72d75b7742
2006-10-12Merge zizzer:/bk/newmemKorey Sewell
into zooks.eecs.umich.edu:/y/ksewell/research/m5-sim/cleanrepo --HG-- extra : convert_revision : 86abc4dabb7c72edc90fae951314d6a6b5c73705
2006-10-12Add test binary & inputsKorey Sewell
--HG-- extra : convert_revision : efc0249ae6f51b9f4f49741aafb2cad21e1fb11e
2006-10-12Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : fa5b2cfa79d87a0612b8116d407a8b2959d9095a
2006-10-12Remove bus and top level parameters from cacheRon Dreslinski
src/mem/cache/base_cache.hh: Remove top level param from cache src/mem/cache/coherence/uni_coherence.cc: Remove top level parameters from the cache --HG-- extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0
2006-10-12Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem.head src/mem/packet.hh: hand merge --HG-- extra : convert_revision : 3f77707360235dc98c6b12a0367ca64a401313df
2006-10-12add a traceflag for functional accessesAli Saidi
implement fix packet and add the ability to print a packet to a ostream remove tabs in packet.hh (Could people stop inserting them??!?!?!) mark const functions in packet.hh as such src/base/traceflags.py: add a traceflag for functional accesses src/mem/packet.cc: implement fix packet and add the ability to print a packet to a ostream src/mem/packet.hh: add the ability to print a packet to an ostream remove tabs in file mark const functions as such --HG-- extra : convert_revision : 4297bce5e1d3abbab48be5bd9eb9e982b751fc7c
2006-10-12Check the response queue on functional accesses.Ron Dreslinski
The response queue is not tying up an MSHR, should we change that or assume infinite storage for responses? src/mem/cache/base_cache.cc: src/mem/tport.cc: Add in functional check of retry queued packets. --HG-- extra : convert_revision : 0cb40b3a96d37a5e9eec95312d660ec6a9ce526a
2006-10-12Another memleak in the memtester (need [] with the delete)Ron Dreslinski
src/cpu/memtest/memtest.cc: Another memleak in the memtester --HG-- extra : convert_revision : f7ab079e90d578fb6b9d1ff238d049fcce55b01b
2006-10-12Fix a memory leak in the memtesterRon Dreslinski
--HG-- extra : convert_revision : 93062b0f1a3ba7a5210e2f27099f20ae8f66522b
2006-10-12Fix problems with unCacheable addresses in timing-coherenceRon Dreslinski
src/base/traceflags.py: src/mem/physical.cc: Add debug falgs fro physical memory accesses src/mem/cache/cache_impl.hh: Snoops to uncacheable blocks should not happen src/mem/cache/miss/miss_queue.cc: Set the size properly on unCacheable accesses --HG-- extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
2006-10-11Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : b6224624ea493531e5ecc161bede7433f96d8a0f
2006-10-11Make default ID unique (not broadcast)Ron Dreslinski
Fix a segfault associated with DefaultId src/mem/bus.cc: Handle a segfault in the bus when DefaultPort was being used src/mem/bus.hh: Make the Default ID more unique (it overlapped with Broadcast ID) --HG-- extra : convert_revision : 9182805c5cf4d9fe004e6c5be8547a8f41ed7bfe
2006-10-11Forgot to mark myself as on the retry listRon Dreslinski
--HG-- extra : convert_revision : c20170320a284a7bf143a929e4d3aa1475a8bfe0
2006-10-11add spec2k testsKorey Sewell
--HG-- extra : convert_revision : 619d6af7013b597ade6440f8cf84d6d099e31763
2006-10-11Fix bus in FS mode.Ron Dreslinski
src/mem/bus.cc: Add debugging statement src/mem/bus.hh: Fix implementation of bus for subsequent recvTimings while handling a retry request. src/mem/tport.cc: Rework timing port to retry properly --HG-- extra : convert_revision : fbfb5e8b4a625e49c6cd764da1df46a4f336b1b2
2006-10-11add bzip test-progKorey Sewell
--HG-- extra : convert_revision : f5197172b094d59ced84423eb34c31ddf23689ee
2006-10-11System not global object, need to preface it with objects.Lisa Hsu
--HG-- extra : convert_revision : 5e105d7082a8c103fb5d5383c3093734bfd590f5
2006-10-11since memoryMode was put into the System (from SimObject), things got broken ↵Lisa Hsu
- this fixes it so that changeToTiming/changeToAtomic works. src/python/m5/SimObject.py: now that setMemoryMode is a method in System, need to convert the SimObject * _ccObject into a system ptr to call setMemoryMode. src/sim/main.cc: need this conversion now. src/sim/sim_object.hh: put the enum back into SimObject. src/sim/system.hh: memoryMode is now a part of SimObject, need the ::'s --HG-- extra : convert_revision : 0ade06957fa57b497798e1f50c237ca1badc821d
2006-10-11some drain changes in timing (kevin's) and some memory mode assertion ↵Lisa Hsu
changes so that when you come out of resume, you only assert if you're really wrong. src/cpu/simple/atomic.cc: memory mode assertion change so that it only goes off if it's supposed to. src/cpu/simple/timing.cc: some drain changes (kevin's) and some changes to memoryMode assertions so that they don't go off when they're not supposed to. --HG-- extra : convert_revision : 007d8610f097e08f01367b905ada49f93cf37ca3
2006-10-11More cache fixes. Atomic coherence now works as well.Ron Dreslinski
src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: Make Memtester able to test atomic as well src/mem/bus.cc: src/mem/bus.hh: Handle atomic snoops properly for cache->cache transfers src/mem/cache/cache_impl.hh: Debug output. Clean up memleak in atomic mode. Set hitLatency. Still need to send back reasonable number for atomic return value. src/mem/packet.cc: Add command strings for new commands src/python/m5/objects/MemTest.py: Add param to test atomic memory. --HG-- extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b
2006-10-11Update for Atomic Coherece with Gabes busRon Dreslinski
--HG-- extra : convert_revision : 6a23052056d1c61cba0a4c77f1030cee419c6fa3
2006-10-11Interesting memtest finally.Ron Dreslinski
Get over 500,000 reads on each of 8 testers before memory leak becomes large. tests/configs/memtest.py: Update test to be more interesting --HG-- extra : convert_revision : 4258b798fbeeed2a376f1bfac100a109eb05620e
2006-10-11Merge zizzer:/n/wexford/x/gblack/m5/newmem_busRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : 70187b8f04d0f8424512f64bdade05bf1aca85a3
2006-10-11Use bus response time paramteresRon Dreslinski
Fix bug with deadlocking src/mem/cache/base_cache.cc: Make sure to not wait anymore --HG-- extra : convert_revision : 5f7b44a1c475820b9862275a0d6113ec2991735d
2006-10-11Don't call recvRetry if the bus is busy anyway. This takes care of a corner ↵Gabe Black
case as well when dealing with grants that aren't used. --HG-- extra : convert_revision : 38f7ef1b41477fb2a2438387ef3a81cccd3e7a8a
2006-10-11Merge zizzer:/n/wexford/x/gblack/m5/newmem_busRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : d2d19b27533f35c6570ee84c6c83b2919f27b97f
2006-10-11Make the bus work if the other sides recvRetry doesn't call sendTiming for ↵Gabe Black
some reason. --HG-- extra : convert_revision : e722ddb0354a5c021dc7c44a3e2f0a64e962442b
2006-10-11When turning asserts into if's don't forget to invert.Ron Dreslinski
src/mem/cache/base_cache.cc: When turning asserts into if's don't forget to invert. Must be too sleepy. --HG-- extra : convert_revision : ea38d5a4b4ddde7b5266b3b2c83bbc256218af9a
2006-10-11Writebacks can be pulled out from under the BusRequest when snoops of ↵Ron Dreslinski
uprgades to owned blocks hit in the WB buffer --HG-- extra : convert_revision : f0502836a79ce303150daa7e571badb0bce3a97a
2006-10-10Only issue responses if we aren;t already blockedRon Dreslinski
--HG-- extra : convert_revision : 511c0bcd44b93d5499eefa8399f36ef8b6607311
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