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2005-05-03Large update of several parts of my code. The most notable change is the ↵Kevin Lim
inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version. SConscript: arch/isa_parser.py: cpu/base_dyn_inst.cc: Remove OOO CPU stuff. arch/alpha/faults.hh: Add fake memory fault. This will be removed eventually. arch/alpha/isa_desc: Change EA comp and Mem accessor to be const StaticInstPtrs. cpu/base_dyn_inst.hh: Update read/write calls to use load queue and store queue indices. cpu/beta_cpu/alpha_dyn_inst.hh: Change to const StaticInst in the register accessors. cpu/beta_cpu/alpha_dyn_inst_impl.hh: Update syscall code with thread numbers. cpu/beta_cpu/alpha_full_cpu.hh: Alter some of the full system code so it will compile without errors. cpu/beta_cpu/alpha_full_cpu_builder.cc: Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters. cpu/beta_cpu/alpha_full_cpu_impl.hh: Update some of the full system code so it compiles. cpu/beta_cpu/alpha_params.hh: cpu/beta_cpu/fetch_impl.hh: Remove asid. cpu/beta_cpu/comm.hh: Remove global history field. cpu/beta_cpu/commit.hh: Comment out rename map. cpu/beta_cpu/commit_impl.hh: Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly. cpu/beta_cpu/cpu_policy.hh: Removed IQ from the IEW template parameter to make it more uniform. cpu/beta_cpu/decode.hh: Add debug function. cpu/beta_cpu/decode_impl.hh: Slight updates for decode in the case where it causes a squash. cpu/beta_cpu/fetch.hh: cpu/beta_cpu/rob.hh: Comment out unneccessary code. cpu/beta_cpu/full_cpu.cc: Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier. cpu/beta_cpu/full_cpu.hh: Updated some of the full system code to make it compile. cpu/beta_cpu/iew.cc: Removed IQ from template parameter to IEW. cpu/beta_cpu/iew.hh: Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue. cpu/beta_cpu/iew_impl.hh: New handling of memory instructions through the Load/Store queue. cpu/beta_cpu/inst_queue.hh: Updated comment. cpu/beta_cpu/inst_queue_impl.hh: Slightly different handling of memory instructions due to Load/Store queue. cpu/beta_cpu/regfile.hh: Updated full system code so it compiles. cpu/beta_cpu/rob_impl.hh: Moved some code around; no major functional changes. cpu/ooo_cpu/ooo_cpu.hh: Slight updates to OOO CPU; still does not work. cpu/static_inst.hh: Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst. kern/kernel_stats.hh: Extra forward declares added due to compile error. --HG-- extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
2005-05-02Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : ac0788599c365b2d7fe0870f0fea4b62c3b3ef22
2005-04-30Merge zizzer:/z/m5/Bitkeeper/m5Ron Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/clean --HG-- extra : convert_revision : eb92d2799c76fad09f6b5a9476e4e9fc7c8dbfca
2005-04-30Handle no_allocates as needing the response in miss_queue, like uncacheablesRon Dreslinski
Add support for hit under miss of a no allocate (It seems as though DMA reads to the same block happen close together, is this an artifact of the header/payload splitting) Make sure to respond to all targets of a no_allocate request --HG-- extra : convert_revision : a9d733f499face4039929524573ffc9500e93d83
2005-04-30Cleanup rcS files. Make sure there are enough tracked connections.Nathan Binkert
Delay before singalling peer to make sure that the peer is ready configs/boot/nat-netperf-server.rcS: delay before singalling to make sure that the natbox is ready configs/boot/nat-netperf-stream-client.rcS: increase the number of tracked connections configs/boot/nat-spec-surge-client.rcS: configs/boot/nfs-client-nhfsstone.rcS: configs/boot/nfs-client-smallb.rcS: configs/boot/nfs-client-tcp-smallb.rcS: configs/boot/nfs-client-tcp.rcS: configs/boot/nfs-client.rcS: configs/boot/nfs-server.rcS: configs/boot/spec-surge-client.rcS: configs/boot/spec-surge-server.rcS: configs/boot/surge-client.rcS: configs/boot/surge-server.rcS: increase the number of tracked connections cleanup configs/boot/nat-spec-surge-server.rcS: configs/boot/natbox-netperf.rcS: configs/boot/nfs-server-nhfsstone.rcS: delay before singalling to make sure that the natbox is ready increase the number of tracked connections cleanup configs/boot/natbox-spec-surge.rcS: delay before singalling to make sure that the natbox is ready increase the number of tracked connections --HG-- extra : convert_revision : 9faa5ec11c9c02fed3d1cff922ca42c41d364204
2005-04-29Add suport for no allocation of cache block on a dma read passing through a ↵Ron Dreslinski
cache from the cpu-side interface --HG-- extra : convert_revision : 0a3b3741924ed39c1c8710d0963e4c8f3e73f81a
2005-04-28Clean up output for pc break events, and remove a unneeded break event.Ron Dreslinski
cpu/pc_event.cc: Add a newline to the printout to clean up output kern/linux/linux_system.cc: Remove the die_if_kernel pc break event, it is being called when not the kernel and leads to unneeded printouts --HG-- extra : convert_revision : c359532db31c961074894cc6c44c8452592caca8
2005-04-28Make ip_conntrack table size largerRon Dreslinski
--HG-- extra : convert_revision : bda54b29cb15144907b186f06517477dea13ba06
2005-04-24Add the m5 parameter to the ns83820 device model so that weNathan Binkert
can pass simulator specific options to the device driver. dev/ns_gige.cc: Add the m5 register and parameter to the ns83820 device model so that we can pass simulator specific options to the device driver. dev/ns_gige.hh: dev/ns_gige_reg.h: Add the m5 register to the ns83820 device model --HG-- extra : convert_revision : 84674887560fa3b607e725b8e5bc8272761fcf09
2005-04-24cleanup mpy fileNathan Binkert
--HG-- extra : convert_revision : ddde8f1b60dfa0c637d82d9217e713f071af6ccb
2005-04-22Make code more portable and port to cygwinNathan Binkert
arch/alpha/alpha_tru64_process.cc: getdirent isn't implemented by cygwin. panic if this function is executed. (It shouldn't be too much to emulate it using opendir, readdir, etc.) arch/alpha/pseudo_inst.cc: Use lseek once and read instead pread. base/intmath.hh: we want int, long, and long long variations of FloorLog2 instead of int32_t, int64_t. Otherwise, we leave one out. base/socket.cc: Fix define that seems to be for apple sim/serialize.cc: don't use the intXX_t stuff, instead, use the real types so we're sure that we cover all of them. --HG-- extra : convert_revision : 9fccaff583100b06bbaafd95a162c4e19beed59e
2005-04-17Mostly hacks for multiplying Frequency-type proxies by constantsSteve Reinhardt
(plus some small fixes). python/m5/config.py: Hacks to allow multiplication on Frequency/Latency-valued proxies. Provide __rmul__ as well as __mul__ on Proxy objects. test/genini.py: Default value for -EFOO should be True not 1 (since 1 is no longer convertable to Bool). --HG-- extra : convert_revision : f8a221fcd9e095fdd7b7db4be0ed0cdcd20074be
2005-04-15Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : febc87fb6083ef8b80a2bc91a766ea9e13d82744
2005-04-14FRon Dreslinski
--HG-- extra : convert_revision : 22245997131432986d94105957461275ee4ae07e
2005-04-14Merge ktlim@zizzer.eecs.umich.edu:/bk/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : 0baadd8d68bfa6f8e96307eb2d4426b0d9e0b8b4
2005-04-13Make multiple calls to SimExit work.Nathan Binkert
--HG-- extra : convert_revision : 91a5652913b7278efe6a3a4955e5e2f723ba59eb
2005-04-13Make the exit after max checkpoints code compile.Nathan Binkert
sim/serialize.cc: call exitNow instead of SimExit. Include the header too. --HG-- extra : convert_revision : 633a8533b23cac914a2b09bd2d3ea5d85243c675
2005-04-13Add support to limit the number of checkpoints dropped.Nathan Binkert
sim/serialize.hh: Add variables to keep track of the number of checkpoints dropped and maximum allowed. --HG-- extra : convert_revision : 32241b90c58def6958ec84c53cc2cca996007506
2005-04-11Fixup split stats.Nathan Binkert
--HG-- extra : convert_revision : 5f3d162c3f4d90f481393f812e6138c659e4f6e2
2005-04-11Update for changes in the way latencies and bandwidths are dealt with.Nathan Binkert
--HG-- extra : convert_revision : 1d183bf47222599ee11154ab0c9eb9cd99a29806
2005-04-11Make the notion of a global event tick independent of the actualNathan Binkert
CPU cycle ticks. This allows the user to have CPUs of different frequencies, and also allows frequencies and latencies that are not evenly divisible by the CPU frequency. For now, the CPU frequency is still set to the global frequency, but soon, we'll hopefully make the global frequency fixed at something like 1THz and set all other frequencies independently. arch/alpha/ev5.cc: The cycles counter is based on the current cpu cycle. cpu/base_cpu.cc: frequency isn't the cpu parameter anymore, cycleTime is. cpu/base_cpu.hh: frequency isn't the cpu parameter anymore, cycleTime is. create several public functions for getting the cpu frequency and the numbers of ticks for a given number of cycles, etc. cpu/memtest/memtest.cc: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/trace/trace_cpu.cc: Now that ticks aren't cpu cycles, fixup code to advance by the proper number of ticks. cpu/memtest/memtest.hh: cpu/trace/trace_cpu.hh: Provide a function to get the number of ticks for a given number of cycles. dev/alpha_console.cc: Update for changes in the way that frequencies and latencies are accessed. Move some stuff to init() dev/alpha_console.hh: Need a pointer to the system and the cpu to get the frequency so we can pass the info to the console code. dev/etherbus.cc: dev/etherbus.hh: dev/etherlink.cc: dev/etherlink.hh: dev/ethertap.cc: dev/ide_disk.hh: dev/ns_gige.cc: dev/ns_gige.hh: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. dev/ide_disk.cc: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. Add some extra debugging printfs dev/platform.cc: dev/sinic.cc: dev/sinic.hh: outline the constructor and destructor dev/platform.hh: outline the constructor and destructor. don't keep track of the interrupt frequency. Only provide the accessor function. dev/tsunami.cc: dev/tsunami.hh: outline the constructor and destructor Don't set the interrupt frequency here. Get it from the actual device that does the interrupting. dev/tsunami_io.cc: dev/tsunami_io.hh: Make the interrupt interval a configuration parameter. (And convert the interval to the new latency/frequency stuff in the python) kern/linux/linux_system.cc: update for changes in the way bandwidths are passed from python to C++ to accomidate the new way that ticks works. For now, we must get the boot cpu's frequency as a parameter since allowing the system to have a pointer to the boot cpu would cause a cycle. kern/tru64/tru64_system.cc: For now, we must get the boot cpu's frequency as a parameter since allowing the system to have a pointer to the boot cpu would cause a cycle. python/m5/config.py: Fix support for cycle_time relative latencies and frequencies. Add support for getting a NetworkBandwidth or a MemoryBandwidth. python/m5/objects/BaseCPU.mpy: All CPUs now have a cycle_time. The default is the global frequency, but it is now possible to set the global frequency to some large value (like 1THz) and set each CPU frequency independently. python/m5/objects/BaseCache.mpy: python/m5/objects/Ide.mpy: Make this a Latency parameter python/m5/objects/BaseSystem.mpy: We need to pass the boot CPU's frequency to the system python/m5/objects/Ethernet.mpy: Update parameter types to use latency and bandwidth types python/m5/objects/Platform.mpy: this frequency isn't needed. We get it from the clock interrupt. python/m5/objects/Tsunami.mpy: The clock generator should hold the frequency sim/eventq.hh: Need to remove this assertion because the writeback event queue is different from the CPU's event queue which can cause this assertion to fail. sim/process.cc: Fix comment. sim/system.hh: Struct member to hold the boot CPU's frequency. sim/universe.cc: remove unneeded variable. --HG-- extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc
2005-04-08Merge zizzer.eecs.umich.edu:/bk/m5Nathan Binkert
into ziff.eecs.umich.edu:/z/binkertn/research/m5/current --HG-- extra : convert_revision : 84720ab5c8123e7bc72b20c877499a0846ea1a4f
2005-04-08full_system no longer exists as a parameterNathan Binkert
--HG-- extra : convert_revision : 173cd24c130cb981036688d9cd8ba3e418d51068
2005-04-08Hand merged a this-> statement for gcc3.4Ron Dreslinski
--HG-- extra : convert_revision : 11daa94a0631da5e9c2e4262a448035491dd86e5
2005-04-08Add Parameter to only do prefetch calculations on data accesses not ↵Ron Dreslinski
instruction accesses --HG-- extra : convert_revision : 85c987561a962f21466f0c1bd0473300d341c398
2005-04-07Hand mergeKevin Lim
base/traceflags.py: Include new flags --HG-- extra : convert_revision : 8017cbe256860dce8b1efc1b4e1e81e883895b90
2005-04-07Include new CPUs.Kevin Lim
--HG-- extra : convert_revision : 710597ae0b84404f0a5b737229391042a15c6e14
2005-04-07Support copying memory requests.Nathan Binkert
--HG-- extra : convert_revision : 783a778e5eeef36eab22a7c855a5474b83ff4488
2005-04-06Add support for acking writes with a configurable delayNathan Binkert
as they are received by the bus bridge. Better Bus debugging. --HG-- extra : convert_revision : c6329384276e0ebcf8ae12b86fddb377af66bbba
2005-04-06fix typo in python config stuffNathan Binkert
python/m5/config.py: fix typo --HG-- extra : convert_revision : 2208453d93149ba4af140dd78c29be4c4943b397
2005-04-06Fix the python NetworkBandwidth conversion functionNathan Binkert
python/m5/convert.py: Fix the NetworkBandwidth conversion function --HG-- extra : convert_revision : 93d9856fe6b59827c116e15835d2ef51292bd6c4
2005-04-06formattingNathan Binkert
--HG-- extra : convert_revision : 0b041556222c3892ee72e4d56c8acdda72bfc303
2005-04-06Cleanup diagnostic and error messages for the IDE diskNathan Binkert
dev/ide_disk.cc: Cleanup diagnostic and error messages --HG-- extra : convert_revision : fb1bc6d9f28a10961c9d3ee1dc81b540b92653b8
2005-04-06Better debugging output for the ide controllerNathan Binkert
dev/ide_ctrl.cc: Better debugging --HG-- extra : convert_revision : 854e17f9f36fe4a0b6b69fd48027d2b1b231e858
2005-04-06Add TcpPort and UdpPort as python typesNathan Binkert
python/m5/objects/SimConsole.mpy: the listener port is a TcpPort --HG-- extra : convert_revision : c26fdd93d3bc35d9f1563ac1087a7f75471c9020
2005-04-06Move back to vmlinux-latestNathan Binkert
--HG-- extra : convert_revision : 9a14f21768f075f0c84f90feebb6d3d897286e34
2005-04-06full_system isn't a useful parameter anymore, get rid of it.Nathan Binkert
python/m5/objects/Root.mpy: sim/universe.cc: util/stats/stats.py: full_system isn't a useful parameter --HG-- extra : convert_revision : 557091be1faa3cf121c55102aba4e6f4c1bd45ef
2005-04-05Minor fixes for g++ 3.4Kevin Lim
--HG-- extra : convert_revision : cb3931c72cfa737414404b7ebebfad7cfea8ef8a
2005-04-04Add more prefetcher support.Ron Dreslinski
SConscript: Add GHB prefetcher to build list python/m5/objects/BaseCache.mpy: Add parameters about when to remove prefetches and wether or not to use cpuid to differentiate access patterns --HG-- extra : convert_revision : 1d3fef21910f2f34b8c28d01b5f6e86eef53357c
2005-04-04Merge zizzer:/z/m5/Bitkeeper/m5Ron Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/prefetcher --HG-- extra : convert_revision : b89d95b6b09a70dc060747f9703643af008c2ddd
2005-04-02Added support for multiple prefetch address from single access (depth of ↵Ron Dreslinski
prefetch) also added the ability to squash some prefetchs to match the GHB technique python/m5/objects/BaseCache.mpy: Added parameters --HG-- extra : convert_revision : 92b646eb61455d283a5c2ac0b3f8fbd62e39fb87
2005-04-02Rework some statistics and add some prefetcher statistics. Also remove an ↵Ron Dreslinski
unneeded function call. --HG-- extra : convert_revision : b40cfc16f237ec03aac15d42fe34d5676b0c71c1
2005-04-02Fix up Python ParamContext support.Steve Reinhardt
--HG-- extra : convert_revision : cd2fe692b42016c4e2a84cd5c8f615c16217254a
2005-04-01Set the time in the request to proprley calculate latenciesRon Dreslinski
--HG-- extra : convert_revision : cd54e924ad89cebbd797beda7dbbdae53eec66a7
2005-04-01Make sure to calculate the new state properly in coherence protocolRon Dreslinski
--HG-- extra : convert_revision : 5a983f5d2e225d4be205faa9bacffc2258452efc
2005-04-01Some hand mergesRon Dreslinski
--HG-- rename : objects/BaseCache.mpy => python/m5/objects/BaseCache.mpy extra : convert_revision : b24ff4c1feb480cf280207d4bbdfe08ef80d1aa2
2005-04-01Another pass at the prefetcher. Now it works with both miss and access ↵Ron Dreslinski
reference streams. Reworked how it is instattiated and how it communicates with other cache objects. SConscript: Compile all the prefetcher files objects/BaseCache.mpy: Add parameters for prefetcher --HG-- extra : convert_revision : 2faa81c17673420ffae72a50a27e310d4c0f4135
2005-04-01Remove a printf that shouldn't be there, Fix some errors with full system ↵Ron Dreslinski
config files that wasn't using coherence in MP cases --HG-- extra : convert_revision : 32670b9252fd4be61ab4dcc8d90f4251d9db5069
2005-03-30Rework the way the prefetcher is used. Now we copy the request from the ↵Ron Dreslinski
prefetch queue and into the mq when issued objects/BaseCache.mpy: Add some parameters for prefetcher --HG-- extra : convert_revision : 1a2e6d2ce5359fab0a4d5d4639a701131101d68c
2005-03-30First pass at a prefetcherRon Dreslinski
SConscript: Add prefetcher to the compilation base/traceflags.py: Add a trace flag for hardware prefetches --HG-- extra : convert_revision : bc210192a2b75b1470b2cd9d5d470fc61cb11315
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